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A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC. 班級 : 積體所碩一 學生 : 林義傑. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003. Outline. INTRODUCTION A typical pipeline architecture Amplifier Sharing Technique Power-Reduction Technique Measurement Results Conclusion.
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A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC • 班級: 積體所碩一 • 學生:林義傑 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 12, DECEMBER 2003
Outline • INTRODUCTION • A typical pipeline architecture • Amplifier Sharing Technique • Power-Reduction Technique • Measurement Results • Conclusion
INTRODUCTION • Sharing an amplifier using FSPI technique • A wide-swing wide-bandwidth telescopic amplifier • an early comparison technique with a constant delay circuit
COMPARISON OF LOW-POWER ARCHITECTURES FOR 10-bit 80-MS/s PIPELINED ADC
POWER-REDUCTION TECHNIQUES • Low-Power High-Bandwidth Opamp • Early Comparison Scheme With Constant Delay Circuit • Low-Offset Dynamic Comparator
CONCLUSION The ADC, which occupies 1.85 mm and only consumes 69 mW at 80 MS/s,has been implemented in a 0.18-um DGO CMOS process technology.