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Collaboration on 65nm technology and its rad tol

Collaboration on 65nm technology and its rad tol. Radiation tolerance. Characteristics to test Vt shifts, Leakage, noise, matching, g m,max , ? Many devices to radiation test: Different transistor sizes and layouts Normal Vt , High Vt , Zero Vt , Low Vt

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Collaboration on 65nm technology and its rad tol

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  1. Collaboration on 65nm technology and its radtol

  2. Radiation tolerance • Characteristics to test • Vt shifts, Leakage, noise, matching, gm,max, ? • Many devices to radiation test: • Different transistor sizes and layouts • Normal Vt, High Vt, Zero Vt, Low Vt • Diodes: band gap reference, temp sensor, etc. • Passives: resistors, capacitors ? • Tracking radtol of foundry over time. • Basic digital libraries: • Standard cells, small standard cells for pixel, Normal Vt, High Vt • RAM • IO • Using at reduced Vdd for extra low power • What can we use in CMS/ATLAS pixels and what de we need to make ? • Parameter corners to be used in simulations • We are clearly out of normal worst case (3sigma) parameter corners • Analog (Spice) , Digital libraries (timing) • Do we need to look at other technologies ?. • Pixels need extreme radiation levels • TID: ~10MGy = 1Grad • NIEL: 1016neu/cm2 • SEU resistant storage cells or TMR. • So far “only basic” radiation qualification done (of TSMC). • Up to ~300Mrad • Signs of interesting/worrying effects above ~300Mrad • Rapidly decreasing gm,maxfp0r Pmos(max drive current) • Memories get hard stock at bits ( Vt shift, Leakage, gm,max, Displacement damage, ?) • Annealing ?. • Neutron/proton test ? • Difference when doing “TID with protons” or do we have a displacement effect ? • Environment • Temperature - Annealing • Many technology options: Baseline: TSMC LP

  3. 65nm Players (radtol) • Collaborations: • ATLAS, CMS, CLIC • AIDA: • Work program defined ? (IP) • To what radiation level ? • EPIX: Awaiting EU funding • Medi/time -pix ?. • Others ? • Groups: • CERN • LBNL • Marseilles-CPPM • Bonn • Padova • Bergamo (analog parameters) • R&D goals ?. • Others ?. • Projects: • CMS pixels • ATLAS pixels • LPGBT • CLIC pixels (low rad.) • CMS track trigger (~100MRad) • Other projects needing same radtol as ATLAS/CMS pixels ?

  4. How to organize 65nm tech/rad work ? • Working group for ATLAS-CMS pixels (+ others ?) • Activities (Work-packages): • Basic devices • Standard cell libraries (custom library ?) • RAM: Leakage, SEU, MBU • Flip-flops/DICE : SEU, MBU • (IO) • Project specific: Pixel prototypes and final chips • Organizing: ATLAS-CMS, AIDA, EPIX, , ? • Pixel Rad hard Working group: • CERN, Marseilles, LBNL, Bonn, Padova = EPIX + ? • What if EPIX not funded ? • Regular (3-6 months) meetings (video) • Defines a workplan and reports activities • Define requirements and what test/qualifications to be made • Collects available test results (and summarize) • Define what still needs to be done (and by whom) • Goal • Radiation test/qualification report • (Library elements), (RAM) • Or everybody just goes along (alone) within their specific project and problems?

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