Design and Implementation of VLSI Systems (EN0160) Lecture 31: Array Subsystems (SRAM)

1. Design and Implementation of VLSI Systems (EN0160) Lecture 31: Array Subsystems (SRAM) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2. SRAM DRAM ROM Array subsystems

3. 2m bits S 0 Word 0 Word 1 A 0 Storage Word 2 A cell 1 A n 1 Decoder - Word N 2 - Word N 1 - n log N = 2 Input-Output ( M bits) Decoder reduces the number of select signals n = log N 2 Array architecture 2m bits S 0 Word 0 S 1 Word 1 S Storage 2 Word 2 cell words N S N 2 - Word N 2 - S N 1 - Word N 1 - Input-Output ( M bits) Intuitive architecture for N x 2m memory Too many select signals: N words == N select signals Problem: ASPECT RATIO or HEIGHT >> WIDTH

4. Array architecture • 2nwords of 2mbits each • If n >> m, fold by 2k into fewer rows of more columns • Good regularity – easy to design • Very high density if good cells are used 3. 2. 1. core 3.

5. Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 λ unit cell 1. Core. 12T SRAM Cell

6. Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline 6T SRAM Cell Size 26 x 45 λ

7. Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip SRAM Read N1 stronger than N2 (N1 has lower resistance)

8. Reading within the context of a column

9. Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter SRAM Write N4 stronger than P2 (N4 has lower resistance)

10. SRAM Column Example

11. n:2n decoder consists of 2n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS 2. Decoders

12. For n > 4, NAND gates become slow Break large gates into multiple smaller gates Large decoders

13. Many of these gates are redundant Factor out common gates into predecoder Saves area Same path effort Predecoding

14. Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing 3. Column circuitry

15. Precharge bitlines high before reads Bit preconditioning and sense amplifiers • Many words in memory • bit capacitance is huge • slow reading (large memory access time) • Sense amplifiers are triggered on small voltage swing (reduce DV)

16. Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers Column multiplexing