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High-Level Synthesis Transformations: Enhancing Hardware Implementation Efficiency

This lecture covers high-level synthesis transformations to improve computational structure flexibility for efficient hardware implementation. Topics include scheduling, estimations, and various transformations like retiming and unfolding for register minimization. The goal is to optimize design for area and clock period minimization. The session also discusses bottleneck identification and enabling principles. High-level synthesis serves as a bridge between behavioral and structural descriptions, offering a high impact on final design outcomes.

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High-Level Synthesis Transformations: Enhancing Hardware Implementation Efficiency

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  1. High-level SynthesisTransformations EE202A (Fall 2003): Lecture #9 Note: Several slides in this Lecture are fromProf. Miodrag Potkonjak, UCLA CS

  2. Overview • High Level Synthesis • Scheduling • Estimations • Transformations

  3. Transformations • Goals of High Level Synthesis • To translate the specification of the algorithm into efficient hardware implementation • The quality of the implementation depends on how the high level synthesis tasks are performed and on the computational structure of the algorithm • Purpose of Transformations • To improve flexibility of the computational structure for the high level synthesis

  4. Transformations

  5. Commutativity, Associativity, Distributivity

  6. Associativity • Associativity is frequently used for tree height reduction

  7. Temporal Transformations D (a) * D (b) = D (a * b)

  8. Retiming

  9. Retiming (contd.)

  10. How does Retiming help? before after

  11. Example of Transformation (Cont’d) • Maximum number of operation that can be executed in a given cycle

  12. Clock Period Minimization • Example; 100 stage lattice filter • Assume add and multiply take 1 and 2 units of time respectively • Critical path in dotted line • Minimum sample period = 105

  13. Clock Period Minimization (contd.) • 2-slowdown version

  14. Clock Period Minimization (contd.) • Retimed version of the 2-slow down model • Critical path = 6 • Minimum sample period = 12

  15. Retiming for Register Minimization

  16. Example of Retiming for Register Minimization

  17. Unfolding

  18. Unfolding (contd.)

  19. How to do Unfolding?

  20. Another Example

  21. How does Unfolding help? • Unfolding a DFG with iteration bound T results in a J-unfolded DFG with iteration bound JT • Seems like no win, but can help with actual sample period in two scenarios • Case 1: sample period could not be made equal to iteration period because of some node with computation time greater than T • Case 2: sample period could not be made equal to iteration period because T is not an integer

  22. Example of Case 1 T=3 Minimum sample period = 4 T=6 Minimum sample period = 6/2=3

  23. Example of Case 2 T=4/3 Minimum sample period = 2 T=4 Minimum sample period = 4/3

  24. Transformations: Bottleneck Identification

  25. Transformations:Enabling Principle

  26. Transformations:How to Improve Designs?

  27. Transformations for Area Optimization

  28. Transformations: Summary • Application Range • Filters are ideal targets for the transformation, since the delays are present in all filter structures • Any problem that includes loops using the previous samples • Side Effects • Transformations leading to a shorter critical path may or may not lead to the minimization of the implementation area • How can we deal with blocks in finding the minimal path or the minimal hardware implementation

  29. Conclusions • High Level Synthesis • Connects Behavioral Description and Structural Description • Scheduling, Estimations, Transformations • High Level of Abstraction, High Impact on the Final Design

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