ENGG3190 Logic Synthesis High Level Synthesis

1. ENGG3190Logic SynthesisHigh Level Synthesis Winter 2014 S. Areibi School of Engineering University of Guelph

2. Outline • Synthesis & Abstraction Levels of Design • High Level Synthesis • Definition • Motivation • Main Preprocessing Steps • Parsing & Analysis • Optimization • Intermediate Forms (DFG/CFG) • Main Processing Steps • Allocation • Scheduling • Binding

3. Synthesis of Digital Circuits High Level Synthesis RTL Logic Synthesis Computational Boolean Algebra Data Structures PCN BDD’s & SAT Algorithms Two Level & Multi Level Logic Synthesis Sequential Logic Synthesis NETLIST (Gates & Wires) Physical Synthesis

4. Abstraction levels Level Behavior Structure Synthesisstep System High-level Logic Physical

5. High-Level Synthesis Could be C, C++, Java, Perl, Python, SystemC, ImpulseC, VHDL, Verilog, etc. High-level Code High-Level Synthesis Custom Circuit Usually a RT VHDL description, but could as low level as a bit file

6. In from memory Controller &a 0 0 2x1 2x1 2x1 a[i] addr acc i 1 128 1 + + < + Done Memory Read acc Memory address High-Level Synthesis acc = 0; for (i=0; i < 128; i++) acc += a[i]; High-Level Synthesis

7. WHILE G < K LOOP F := E*(A+B); G := (A+B)*(C+D); END LOOP; Algorithm Controller PLA Latches High Level Synthesis Library + - Constraints Area Time: Clock Period Nr. of clock steps Power * < Datapath K X < A C B D E Y + * F G

8. Goal of High Level Synthesis From Behavioral specification at ‘System Level’(Algorithms) To Structural implementation at ‘Register Transfer Level’ of Data path (ALU’s, REG’s, MUX’s) and Controller • Optimize Area, Performance, Power, … • Abide by constraints, • Generally restricted to a single process • Generally data path is optimized; controller is by-product

9. Architectural versus Logic Synthesis • Transform behavioral into structural view. • Behavioral-level synthesis: • Architectural abstraction level (Algorithm). • Determine macroscopicstructure (RTL). • Example of synthesis: major building blocks. • Logic-level synthesis: • Logic abstraction level (Boolean Equations). • Determine microscopicstructure (Gates). • Example of synthesis: logic gate interconnection.

10. Level of Automation must go up? Why?

11. Architectural-level synthesis motivation • Raise input abstractionlevel. • Reduce specification of details (hides them). • Extend designer base. • Self-documenting design specifications. • Ease modifications and extensions (Portability) • Reduce design time. • Rely on synthesis compilers to produce RTL • Faster to verify our designs at Arch Level • Explore and optimize macroscopic structure: • Series/parallel execution of operations. • Reduce power consumption (better algorithms)

12. Design Space Exploration We consider here totally different architectures Delay Arch I Arch II Arch III Area

13. Design Space Exploration: Multi Objective Optimization Area Area Area Area Max Cycle-time Latency Latency Latency Latency Max

14. Stages of architectural-level synthesis • Translate HDL or C/C++ models into: • Data Flow Graphs, • Sequencing Graphs. • Behavioral-level optimization: • Optimize abstract models independently from the implementation parameters. • Architectural synthesis and optimization: • Create macroscopic structure: • data-pathand control-unit. • Consider area and delay information of the implementation. (on the global level)

16. HLS Flow High-level Code Converts code to intermediate representation - allows all following steps to use language independent format. Front-end Syntactic Analysis Intermediate Representation Optimization Determines when each operation will execute, and resources used Scheduling/Resource Allocation Back-end Maps operations onto physical resources Binding/Resource Sharing Controller + Datapath

17. Analysis and Parsing

18. Syntactic Analysis • Definition: Analysis of code to verify syntactic correctness • Converts code into intermediate representation • 2 steps • 1) Lexical analysis (Lexing) • 2) Parsing High-level Code Lexical Analysis Syntactic Analysis Parsing Intermediate Representation

19. Lexical Analysis • Lexical analysis (lexing) • Breaks code into a series of defined tokens • Token: defined language constructs x = 0; if (y < z) x = 1; Lexical Analysis ID(x), ASSIGN, INT(0), SEMICOLON, IF, LPAREN, ID(y), LT, ID(z), RPAREN, ID(x), ASSIGN, INT(1), SEMICOLON

20. Lexing Tools • Define tokens using regular expressions - outputs C code that lexes input • Common tool is “lex” /* braces and parentheses */ "[" { YYPRINT; return LBRACE; } "]" { YYPRINT; return RBRACE; } "," { YYPRINT; return COMMA; } ";" { YYPRINT; return SEMICOLON; } "!" { YYPRINT; return EXCLAMATION; } "{" { YYPRINT; return LBRACKET; } "}" { YYPRINT; return RBRACKET; } "-" { YYPRINT; return MINUS; } /* integers [0-9]+ { yylval.intVal = atoi( yytext ); return INT; }

21. Parsing • Performs analysis on token sequence to determine correct grammatical structure • Languages defined by context-free grammar Correct Programs Grammar x = 0; y = 1; x = 0; Program = Exp if (a < b) x = 10; Exp = Stmt SEMICOLON | IF LPAREN Cond RPAREN Exp | Exp Exp if (var1 != var2) x = 10; Cond = ID Comp ID x = 0; if (y < z) x = 1; x = 0; if (y < z) x = 1; y = 5; t = 1; Stmt = ID ASSIGN INT Comp = LT | NE

22. Parsing Incorrect Programs Grammar x = 3 + 5; Program = Exp Exp = S SEMICOLON | IF LPAREN Cond RPAREN Exp | Exp Exp x = 5 x = 5;; if (x+5 > y) x = 2; Cond = ID Comp ID x = y; S = ID ASSIGN INT Comp = LT | NE

23. Parsing Tools • Define grammar in special language • Automatically creates parser based on grammar • Popular tool is “yacc” - yet-another-compiler-compiler program: functions { $$ = $1; } ; functions: function { $$ = $1; } | functions function { $$ = $1; } ; function: HEXNUMBER LABEL COLON code { $$ = $2; } ;

24. Overview of Hardware Synthesis converts the program text file into strings of tokens. Tokens can be specified by regular expressions. In the UNIX world, the “lex” tools are popular for this. • The syntax of a programming language is specified by a grammar. (A grammar defines the order and types of tokens.) This analysis organized streams of tokens into an abstract syntax tree.

25. Overview of Hardware Synthesis analyze the semantics, or meanings, of the program. Generate a symbol table. Check for uniqueness of symbols and information about them. determine the order and organization of operations

26. Intermediate Representations DFG/CDFG

27. Intermediate Representation • Parser converts tokens to intermediate representation • Usually, an abstract syntax tree Assign x = 0; if (y < z) x = 1; d = 6; x if 0 assign cond assign y z < x d 1 6

28. Intermediate Representation • Why use intermediate representation? • Easier to analyze/optimize than source code • Theoretically can be used for all languages • Makes synthesis back end language independent Java Perl C Code Syntactic Analysis Syntactic Analysis Syntactic Analysis Intermediate Representation Scheduling, resource allocation, binding, independent of source language - sometimes optimizations too Back End

29. Intermediate Representation • Different Types • Abstract Syntax Tree • Data Flow Graph (DFG) • Sequencing Graph (DFG with Source and Sink) • Control Flow Graph (CFG) • Control/Data Flow Graph (CDFG) • CDFG  Combines control flow graph (CFG) and data flow graph (DFG) * * + Data Flow Graph Control Flow Graph

30. Data Flow Graph • Definition • A directed graph that shows the data dependencies between a number of functions • G = (V,E) • Nodes (V): each node having input/output data ports • Arces (E): connections between the output ports and input ports • Semantics • Fire when input data are ready • Consume data from input ports and produce data to its output ports • There may be many nodes that are ready to fire at a given time

31. Data Flow Graphs • DFG • Represents data dependencies between operations c b a d * + x = a+b; y = c*d; z = x - y; - z y x

32. b 4 c a 2 x x -1 ** x - sqrt + - / / X2 X1 Constant Multiplication Square root Division Nodes of DFG can be any operators, also very complex operators

33. original code: x  a + b; y  a * c; z  x + d; x  y - d; x  x + c; Data flow graph construction c d b a + * + + - x y z x x

34. original code: x a + b; y  a * c; z x + d; x y - d; xx + c; single-assignment form: x1 a + b; y  a * c; z x1 + d; x2 y - d; x3x2 + c; Data flow graph construction

35. single-assignment form: x1 a + b; y  a * c; z x1 + d; x2 y - d; x3 x2 + c; c d b a + * - + y x1 + z x2 x3 Data flow graph construction

36. NOP NOP + + + + < < * * * * * * * * * * * * Sequencing Graph • Add source and sink nodes (NOP) to the DFG Data Flow Graph (DFG) Required for some Scheduling Algorithms Sequencing Graph

37. Control Flow Graphs • CFG • Represents control flow dependencies of basic blocks • Basic block is section of code that always executes from beginning to end • I.e. no jumps into or out of block acc=0, i = 0 acc = 0; for (i=0; i < 128; i++) acc += a[i]; if (i < 128) Done acc += a[i] i ++

38. Control/Data Flow Graph • CDFG  Combines CFG and DFG • Maintains DFG for each node of CFG acc = 0; for (i=0; i < 128; i++) acc += a[i]; 0 0 acc i acc=0; i=0; if (i < 128) a[i] acc i 1 Done acc += a[i] i ++ + + i acc

39. Control/Data Flow Graph • Definition • A directed graph that represents the control dependencies among the functions • branch • fall-through • G=(V,E) • Nodes (V) • Encapsulated DFG • Decision • Arcs (E) • flow of the controls • Very similar to FSMD • Operation rectangles (instructions) can be vary complicated • Diamonds for predicates can be very complicated and require many clock pulses to complete.

40. fun0 Y N fun1 cond1 fun2 fun3 test1 fun4 fun5 fun6 fun7 CDFG Example fun0(); if (cond1) fun1(); else fun2(); fun3(); switch(test1) { case 1: fun4(); break; case 2: fun5(); break; case 3: fun6(); break; } fun7();

41. Summary • Data Flow Graph (DFG) • models data dependencies. • Does not require that nodes be fired in a particular order. • Models operations in the functional model—no conditionals. • Allocation and Mapping • Scheduling – ASAP, ALAP, List-based scheduling • Control/Data Flow Graph • Represents control dependencies

42. High-Level Synthesis:Optimization

43. Synthesis Optimizations • After creating CDFG, high-level synthesis optimizes graph • Goals • Reduce area • Improve latency • Increase parallelism • Reduce power/energy • 2 types • Data flow optimizations • Control flow optimizations

44. Behavioral Optimization

45. Data Flow Optimizations • Tree-height reduction • Generally made possible from commutativity, associativity, and distributivity a b c d c d a b + + + + + + c d a b b a c d * + * + + +

46. Tree-height reductionusing commutativity and associativity x = ( a + (b *c ) ) + d x = (a +d) + (b *c) No Change in Resources

47. Tree-height reduction using distributive .. x = a * (b * c * d +e) x = (a * b) * (c * d) + (a e); Increase in Resources Required

48. Data Flow Optimizations • Operator Strength Reduction • Replacing an expensive (“strong”) operation with a faster one • Common example: replacing multiply/divide with shift 0 multiplications 1 multiplication b[i] = a[i] << 3; b[i] = a[i] * 8; c = b << 2; a = b + c; a = b * 5; a = b * 13; c = b << 2; d = b << 3; a = c + d + b;

49. Data Flow Optimizations • Constant propagation • Statically evaluate expressions with constants x = 0; y = x * 15; z = y + 10; x = 0; y = 0; z = 10;

50. Examples of propagation • First Transformation type: Constant propagation: • a = 0, b = a +1, c = 2 * b, • a = 0, b = 1, c = 2, • Second Transformation type: Variable propagation: • a = x, b = a +1, c = 2 * a, • a = x, b = x +1, c = 2 * x,