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First Wafer Results from Aptasic

First Wafer Results from Aptasic. Vladimir Zivkovic NIKHEF. FE-I4 testing meeting Amsterdam, January 9-th 2012. Test Development for Wafer Test in Industrial environment. Test patterns pre-verified at CERN on 4 boards with wire-bonded chips on Credence Sapphire platform,

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First Wafer Results from Aptasic

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  1. First Wafer Results from Aptasic Vladimir Zivkovic NIKHEF FE-I4 testing meeting Amsterdam, January 9-th 2012

  2. Test Development for Wafer Test in Industrial environment • Test patterns pre-verified at CERN on 4 boards with wire-bonded chips on Credence Sapphire platform, • Aptasic created the probe card for wafer test for their Credence Diamond Platform, • One of the CERN boards with golden device verified at Aptasic environment prior to the wafer test (with hardware adapter), • Wafer test performed at Aptasic during the last week of 2011. 1 probed wafer : V3ABA5H 3 virgin wafers: V5AKGRH, VCAQMBH, V0AK42H

  3. Test Sequence and the distribution chart • Continuity test (pin connectivity, ESD protection diodes) • Power Supply Test • Scan Test (using the DfT with scan chains) in EOCHL, DOB, CMD • IDDQ Test (using the DfT with scan chains) in EOCHL, DOB

  4. Wafer Map V3ABA5H • Not as bad as it looks like : • Power supply test limits might have been too tight (when the current is measured at 20.001mA, the chip is deemed as failed) • The same continuity test • IDDQ test may have produced a few outliers (see following slides) • Scan test (in red) are the chips with fault

  5. Individual Test result distribution results – an example : IDDQ EOCHL Test

  6. Datalog

  7. Datalog (II)

  8. Datalog (III)

  9. Wafer Map Comparison Chips 12, 30, 54, 58, 60 were the test escapes in Bonn Chips 9, 16, 17, 26, 27, 38 escaped the test at Aptasic Other (parametric) mismatches require further analysis

  10. Test Results from the other wafers

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