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ELEC 2200-002 Digital Logic Circuits Fall 2014 Delay and Power

This lecture explains the concepts of delay and power in digital logic circuits, including rise time, fall time, gate delay, and propagation delay. It also discusses capacitances in MOSFETs and the charging of capacitors. The lecture concludes with an introduction to static timing analysis and path analysis algorithms.

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ELEC 2200-002 Digital Logic Circuits Fall 2014 Delay and Power

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  1. ELEC 2200-002Digital Logic CircuitsFall 2014Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC2200-002 Lecture 8

  2. Delay: Definitions • Rise time is the time a signal takes to rise from 10% to 90% of its peak value. • Fall time is the time a signal takes to drop from 90% to 10% of its peak value. • Delay of a gate is the time interval between the input crossing 50% of peak value and the output crossing 50% of peak value. VDD GND 90% VDD B Fall time 10% VDD A Time 1→1 1→0 C Gate delay NAND gate VDD GND B 0→1 90% VDD C Rise time 10% VDD ELEC2200-002 Lecture 8 Time

  3. Consider Delay of Inverter(Other Gates are Similar) VDD Source C1 Drain 0→1 1→0 In Out → to fanout gates Drain C2 CW + C G-in Source GND ELEC2200-002 Lecture 8

  4. Capacitances in MOSFET L = Channel length (fixed) W = Width (transistor size) tox = Oxide thickness W Cgs Cgd Gate Gate oxide Source Drain L Cg Cd Cs Bulk R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, 2008. ELEC2200-002 Lecture 8

  5. Gate Capacitance Cg = εoxWL / tox = Cpermicron W εox Cpermicron = ── L tox where εox=3.9ε0 for Silicon dioxide = 3.9 × 8.85 × 10-14 F/cm ELEC2200-002 Lecture 8

  6. Propagation Delay of a Transition VDD Ron ic(t) vi (t) vo(t) CL R = large Ground CL = Total load capacitance for gate; includes transistor capacitances of driving gate + routing capacitance + transistor capacitances of driven gates; obtained by layout analysis. ELEC2200-002 Lecture 8

  7. Charging of a Capacitor R = Ron t = 0 v(t) i(t) C = CL VDD Charge on capacitor, q(t) = C v(t) Current, i(t) = dq(t)/dt = C dv(t)/dt ELEC2200-002 Lecture 8

  8. i(t) = C dv(t)/dt = [VDD – v(t)] /R dv(t) dt ∫───── = ∫ ──── VDD – v(t) RC – t ln [VDD – v(t)] = ── + A RC Initial condition, t = 0, v(t) = 0 → A = ln VDD – t v(t) = VDD[1 – exp(───)] = 0.5VDD RC t = 0.69 RC ELEC2200-002 Lecture 8

  9. Inverter: Idealized Input VDD GND INPUT Gate delay VDD 0.5VDD GND OUTPUT time t= 0 0.69CR ELEC2200-002 Lecture 8

  10. Large Circuit Timing Analysis • Determine gate delays: • From layout analysis, or use approximate delays: • Gate delay increases in proportion to number of fanouts (increased capacitance) • Delay decreases in proportion to gate size increase (reduced transistor channel resistance) • Purpose of analysis is to verify timing behavior – determine maximum speed of operation. • Methods of analysis: • Circuit simulation – most accurate, expensive (Spice program) • Event-driven logic simulation – efficient, accurate • Static timing analysis (STA) – most efficient, approximate ELEC2200-002 Lecture 8

  11. Static Timing Analysis (STA) • Combinational logic for critical path delays. • Circuit represented as an acyclic directed graph (DAG). • Gates characterized by delays. • No inputs are used – worst-case analysis – static analysis (simulation is dynamic). ELEC2200-002 Lecture 8

  12. Example Levelize graph. Initialize arrival times at primary inputs to 0. 0 0 A 1 H 3 Gate delay 0 0 B 3 E 1 G 2 0 0 C 1 J 1 F 1 0 0 D 2 Level of a gate is one greater than the maximum of fanin gate levels Level 0 1 2 3 4 5 ELEC2200-002 Lecture 8

  13. Example (Cont.) Determine output arrival time when all input arrival times are known. 0 0 A 1 1 10 H 3 Largest of input delays + gate delay 0 0 B 3 3 4 E 1 7 G 2 0 0 C 1 1 8 J 1 5 F 1 0 0 2 D 2 Level 0 1 2 3 4 5 ELEC2200-002 Lecture 8

  14. Example (Cont.) Trace critical path from the output with longest arrival time. 0 0 A 1 1 10 H 3 Critical path Delay = 10 0 0 3 B 3 4 E 1 7 G 2 0 0 C 1 1 8 J 1 5 F 1 0 0 2 D 2 Level 0 1 2 3 4 5 ELEC2200-002 Lecture 8

  15. Path Analysis Algorithms for Directed Acyclic Graphs (DAG) • Graph size: n = |V| + |E|, for |V| vertices and |E| edges. • Levelization: O(n) (linear-time) algorithm finds the maximum (or minimum) depth. • Path counting: O(n2) algorithm. Number of paths can be exponential in n. • Finding all paths: Exponential-time algorithm. • Shortest (or longest) path between two nodes: • Dijkstra’s algorithm: O(n2) • Bellman-Ford algorithm: O(n3) ELEC2200-002 Lecture 8

  16. References • Delay modeling, simulation and testing: • M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000. • Analysis and Design: • G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994. • N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999. • PrimeTime (Static timing analysis tool): • H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition, Springer, 2002 ELEC2200-002 Lecture 8

  17. CMOS Logic (Inverter) VDD No current flows from power supply! Where is power consumed? GND F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid-State Circuits Conference Digest, vol. IV, February 1963, pp. 32-33. ELEC2200-002 Lecture 8

  18. Components of Power • Dynamic, when output changes • Signal transitions (major component) • Logic activity • Glitches • Short-circuit (small) • Static, when signal is in steady state • Leakage (used to be small) Ptotal = Pdyn + Pstat = Ptran +Psc+Pstat ELEC2200-002 Lecture 8

  19. Charging of Output Capacitor • From Slide 8: – t v(t) = V [1 – exp(── )] RC dv(t) V – t i(t) = C ─── = ── exp(── ) dt R RC ELEC2200-002 Lecture 8

  20. Total Energy Per Charging Transition from Power Supply ∞∞ V 2 – t Etrans = ∫ V i(t) dt = ∫ ── exp(── ) dt 00 R RC = CV 2 ELEC2200-002 Lecture 8

  21. Energy Dissipated Per Transition in Transistor Channel Resistance ∞ V 2∞ -2t R ∫ i2(t) dt = R ── ∫ exp(── ) dt 0 R20 RC 1 = ─ CV 2 2 ELEC2200-002 Lecture 8

  22. Energy Stored in Charged Capacitor ∞ ∞ - t V - t ∫ v(t) i(t) dt = ∫ V [1-exp(── )]─ exp(── ) dt 00 RC R RC 1 = ─ CV 2 2 ELEC2200-002 Lecture 8

  23. Transition Power • Gate output rising transition • Energy dissipated in pMOS transistor = CV 2/2 • Energy stored in capacitor = CV 2/2 • Gate output falling transition • Energy dissipated in nMOS transistor = CV 2/2 • Energy dissipated per transition = CV 2/2 • Power dissipation: Ptrans = Etransα fck = α fck CV 2/2 α = activity factor fck = clock frequency ELEC2200-002 Lecture 8

  24. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage GLITCH Delay=2 2 0 Delay =1 1 3 0 Ptotal = Pdyn+ Pstat = Ptran + Psc+ Pstat ELEC2200-002 Lecture 8

  25. Short Circuit Power of a Transition: Psc VDD isc(t) vi (t) vo(t) CL Ground ELEC2200-002 Lecture 8

  26. Short-Circuit Power • Increases with rise and fall times of input. • Decreases for larger output load capacitance; large capacitor takes most of the current. • Small, about 5-10% of dynamic power; momentary shorting of supply and ground during opening and closing of transistor switches. ELEC2200-002 Lecture 8

  27. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage ELEC2200-002 Lecture 8

  28. Static (Leakage) Power • Reason: Resistance of an open transistor switch is large but not infinite. • Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. • For a gate it is a small fraction of the total power; it can be significant for very large circuits. • Static power increases as feature size is scaled down; controlling leakage is an important aspect of transistor design and semiconductor process technology. ELEC2200-002 Lecture 8

  29. CMOS Gate Power Output signal transition Dynamic current Short-circuit current Leakage current v(t) V R = Ron i(t) vi (t) v(t) i(t) Large resistance C isc(t) isc(t) Ground Leakage current time ELEC2200-002 Lecture 8

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