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SYEN 3330 Digital Systems

SYEN 3330 Digital Systems. Chapter 6 – Part 4. Overview of Chapter 6. Types of Sequential Circuits Storage Elements Latches Flip-Flops Sequential Circuit Analysis State Tables State Diagrams Sequential Circuit Design Specification Assignment of State Codes Implementation

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SYEN 3330 Digital Systems

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  1. SYEN 3330 Digital Systems Chapter 6 – Part 4 SYEN 3330 Digital Systems

  2. Overview of Chapter 6 • Types of Sequential Circuits • Storage Elements • Latches • Flip-Flops • Sequential Circuit Analysis • State Tables • State Diagrams • Sequential Circuit Design • Specification • Assignment of State Codes • Implementation • HDL Representation SYEN 3330 Digital Systems

  3. Developing the State Diagram SYEN 3330 Digital Systems

  4. Developing the State Diagram SYEN 3330 Digital Systems

  5. Sequence Recognizer Procedure SYEN 3330 Digital Systems

  6. Sequence Recognizer Example SYEN 3330 Digital Systems

  7. Example: Recognize 1101 SYEN 3330 Digital Systems

  8. Recognize 1101 (Continued) SYEN 3330 Digital Systems

  9. Recognize 1101 (Continued) SYEN 3330 Digital Systems

  10. Recognize 1101 (Continued) SYEN 3330 Digital Systems

  11. Complete the Diagram (1101) SYEN 3330 Digital Systems

  12. Add Missing Arcs SYEN 3330 Digital Systems

  13. 1101 State Table from Diagram From State A, the “0” and “1” input transitions have been filled in along with the outputs. SYEN 3330 Digital Systems

  14. Complete 1101 State Table SYEN 3330 Digital Systems

  15. Moore Model for 1101 SYEN 3330 Digital Systems

  16. Moore Diagram for 1101 SYEN 3330 Digital Systems

  17. Moore State Table for 1101 SYEN 3330 Digital Systems

  18. Second State Diagram Example • A register consists of an ordered set of n flip-flops plus combinational logic to determine its next state. • If a register can be designed as a set of n identical cells, the register cell can be designed as a two-state sequential circuit. • Next we will consider such as example. SYEN 3330 Digital Systems

  19. Data_in (7:0) CLS Register(7:0) LDS RESET (Async) CLK Data_out(7:0) Parallel Load Register with Synchronous Clear and Load • Register Specification • Diagram: • Table: SYEN 3330 Digital Systems

  20. Data_in (i) CLS Reg. Cell(i) LDS FF CLK Data_out(i) RESET (Async) Second Example:Register Cell Design • By definition, a register cell is a sequential circuit that: • contains one flip-flop (2 states) • has the flip-flop output as the primary external register output (Moore model) • Cell Diagram: SYEN 3330 Digital Systems

  21. A/0 A/0 RESET RESET Second Example:State Diagram Design • Initial State: • Add Load: • Add Clear: State/Data_out(i) 1, 0 1, 1 LDS,Data_in B/1 1, 0 1, 1 0, 1, 0; 1, -, - State/Data_out(i) CLS,LDS,Data_in 0, 1, 1 A/0 B/1 RESET 0,1,0; 1,-,- 0,1,1 SYEN 3330 Digital Systems

  22. Second Example:State Diagram Design • Make the state unchanged (Hold Reg) by adding all unused input combinations for each state. CLS,LDS,Data_in State/Data_out(i) 0, 1, 0; 1, -, - 0, 1, 1 A/0 B/1 RESET 0,1,1; 0,0,- 0,1,0; 1,-,-; 0,0,- SYEN 3330 Digital Systems

  23. Second Example: State Table • From State Diagram: CLS, LDS, Data_in SYEN 3330 Digital Systems

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