Calibrating Achievable Design

1. Calibrating Achievable Design Andrew B. Kahng GSRC Executive Review 9/19/02 Theme Members: Wayne Dai, Tsu-Jae King, Wojciech Maly, Igor Markov, Herman Schmit, Dennis Sylvester

2. Outline • The Problem: Design Technology Productivity • The Value Proposition: Focus x TTM x QOR x Impact x … • Specific Projects: Accomplishments and Plans • Collaboration and Roadmap

3. Problem: Design Technology Productivity Gap • ITRS-2001: “Cost of design is the greatest threat to the semiconductor roadmap” • interoperability, design quality and cost metrics, design process optimization • Design Productivity Gap = Design Technology Productivity Gap • This Theme: improve Design Technology Productivity by providing open, shared infrastructures that change how we specify, develop, and measureandimprove Design Technology • Address both design complexity and design technology complexity • Synergy: {Correct R&D focus} x {Faster TTM} x {Validated QOR improvement} • Living Roadmap: Shared “red bricks” to optimize SEMI R&D investment • New cultures: open-source publication, CAD-IP reuse, METRICS benchmarking

4. Calibrating Achievable Design (C.A.D.) Theme • GTX / Living Roadmap: Where to Focus? • What is the benefit of low-k? • Achievable global signaling quality? • Optimal memory integration and architecture? • http://vlsicad.ucsd.edu/GTX • CAD-IP Reuse: Faster and Better R&D • Industry-compatible, open-source, back-end flows • http://vlsicad.eecs.umich.edu/BK • Remote execution “autograding” infrastructure • (VLSI design education, common data model, …) • METRICS: Measure & Improve • Design metrics, design project metrics • Clock speed, front-end acceptance, tool noise, … • Deployed in industry • http://vlsicad.ucsd.edu/METRICS

5. The Value Proposition • Not Business As Usual • Design (Technology) Productivity Gap is the critical challenge • Launch FRC-scale initiatives that impact entire community, industry • Culture changes: publication standards and evaluation methodologies, creation of reusable CAD-IP, open-source, self-consistent roadmapping, … • Living Roadmap and proactive involvement within ITRS community: ORTCs, System Drivers, analyses of “shared red bricks”, … • Bookshelf: 30 slots, 100+ entries, 1000’s of downloads, clear impact across academic literature (DAC, ICCAD, ISPD, IWLS, …), in industry (Capo source is free and open; actively used at > 10 companies) • METRICS: integrated into commercial iCadence platform, used at TI, 20+ attendees at DAC-2002 BOF meeting • Next: Education, Cost-Driven Design, …

6. Specific Projects (1) GSRC Technology Extrapolation (GTX) “Living Roadmap”

7. Progress in Technology Extrapolation • “Living ITRS” • ITRS-2001 (December 2001): consistency of power, die size, density, performance parameters, spanning PIDS, A&P, Test, Design, ORTCs • GTX distribution on SEMATECH website (linked to ITRS-2001) • Integrated with other models (SUSPENS, BACPAC, …) • Mantra: “Shared Red Bricks” (synergy among SEMI R&D programs) • New understanding of key axes in achievable design envelope • Cost-driven integration and packaging (UCSC) • Interconnect (Michigan, UCB, UCSD, UCSC) • Variability (Michigan, UCSD) • Power (via PED Theme, UCB, Michigan)

8. Logic&Buffer Logic&Buffer ESD Protection Circuit PAD PAD Cost-Driven Integration and Packaging (UCSC) • Area-IO advantages • Preserves on-chip electrical environment in the SIP context • Minimizes size of ESD protection device for intra-package IO’s • Improved signal integrity due to power and ground pad structure • Testbed: Single-Package Computer • Integrated CPU, North Bridge, graphics chip, DDR SDRAM • Balance: core logic, memory access speeds • Other issues: rerouting wirelength, IO performance, thermal performance, cost, … Area-IO Conventional IO

9. Attractive CLC electrical characteristics Maximum off-chip delay << IO buffer delay (3.5ns) Signal round trip time < rise time (500ps) Inter-chip skew < board skew (500ps) No terminating resistors required Smaller IO buffer size and minimized ESD protection Chip-Laminate-Chip Memory Integration Laminate Logic Decoupling C BGA ball Area-IO DRAM Chip-Laminate-Chip (CLC) architecture Source: SyChip Inc. • DAchievable envelope = ? • Routability of IO redistribution? • Optimal power-ground structure on laminate? • Optimal clock structure on laminate? • Model of junction temperature in SIP? • Cost? 3.85 mm • Design calibration • Configurable Area-IO SRAM ( 3.34M Tr., 570 Area-IO ) 6.80 mm

10. Multi-GHz On-Chip Interconnects (UCB) • Loop-based model for fully-shielded global clock structure* • Highly efficient extraction of loop RLC values • Models verified with full-wave simulation and measurement data • Available in GTX • Closed-form interconnect performance model** • Driver delay and rise time • Interconnect delay, rise time and overshoot • Available in GTX • Design Optimization*** • Design guidelines for best interconnect structure for optimal delay and power * Xuejue Huang, Phillip Restle, Thomas Bucelot, Yu Cao, and Tsu-Jae King, "Loop-based Interconnect Modeling and Optimization Approach for Multi-GHz Clock Network Design", Custom Integrated Circuits Conference (CICC), pp. 19-22, 2002 ** Xuejue Huang, Yu Cao, Dennis Sylvester, Tsu-Jae King, and Chenming Hu, "Analytical Performance Models for RLC Interconnects and Application to Clock Optimization", to be presented at International ASIC-SoC conference, September 2002, Rochester, USA. *** submitted to JSSC UCB, 2002

11. Active Shields (Michigan) • Repeater, shielding paradigms entrenched in high-perf flow • Seek complementary “drop-in” techniques that improve delay, slope, power, noise immunity • Actively useshields to minimize capacitance or inductance • Switch shields to improve signal propagation and/or noise immunity • For RC lines, switch shields in phase with signal net to reduce effective coupling cap, delay • For inductive lines, switch shields in opposite phase with signal net to produce better return path, reduce loop inductance

13. Interconnect Architecture Metrics, Optimization (UCSD) • Example motivation: “Is low k worth it?” • New interconnect architecture metric allows quantified comparison of design, process, and materials technology improvements • Sensitive to entire interconnect stack, repeater area budget, design wirelength distribution, clock frequency, per-connection delay targets, … TSMC 90nm node:Improving Miller coupling factor by 38% (better design, shielding) equivalent to 40% improvement in k

14. Specific Projects (2) CAD-IP Reuse via TheGSRC Bookshelf Pervasive Automation via bookshelf.exe

15. Previous Mindset: CAD-IP Reuse • CAD-IP Reuse: One of three original initiatives in CAD Theme • “Trivial idea”  GSRC Bookshelf • Reuse helps, but is not a panacea • Consider: Moore’s Law + Design Productivity Crisis required asymptotics of computational and design effort • Near-linear memory: design hierarchy, coarse views • Near-linear runtime: fast global optimization heuristics • Near-linear design effort: auto-installation, all-pairs benchmarking, design flow health monitoring • Near-linear learning curve: “autograders”, open-source •  CAD-IP Reuse is one asymptotic requirement

16. The VLSI CAD Bookshelf • GSRC-provided service that supports near-linear scaling of complexity in EDA (= a repository) • Growing popularity is seen from downloads and contributions • Algorithm descriptions and analyses; open-source CAD tools • Open design benchmarks and algorithm comparisons • Currently 30 slots, 100+ entries: Verilog Tools through Clock Skew Scheduling • Described in IEEE Design and Test, May/June 2002 • Growing adoption within academic literature, review process • ISPD 2002 papers from UCLA, UCSD, Michigan • DAC 2002 papers from Michigan and UIC • ICCAD 2002 papers from IBM, UCSB and Michigan • Ongoing work at CMU, UCSD, Minnesota, etc. • Many fresh Ph.D.s in CAD are now familiar with the Bookshelf

17. Industry Usage of the GSRC Bookshelf • Common denominator in discussions with academia • Intel(Santa Clara) and IBM (Austin and T.J. Watson) • Downloaded and compiled several tools from the Bookshelf • Wrote parsers/converters (~2 weeks of time), distributed internally • Compared to internal tools on internal benchmarks  “results on par or better” • Tools in use for comparisons and algorithm design experiments • Cadence Design Systems (San Jose and NJ) • Downloaded and compiled several tools from the Bookshelf • In some cases (where LEF/DEF was not available) wrote converters • Used for prototyping and evaluation of new commercial tools • Other companies • Prototyping design flows before full-blown tools are ready • Many repeated downloads, but little technical feedback (no feedback or fee required by our license)

18. Academic Usage of the GSRC Bookshelf • New floorplanning methodology for pipelined array designs developed at CMU, based on “wire path length” metric • Bookshelf usage • “Classic” = Bookshelf Block Floorplanner • “Classic+LSP” and “New” methods built on same Bookshelf code • Discovery: new floorplanning methodology yields faster and smaller pipelined designs • Less area wasted on hold time fixing than in unfloorplanned designs • Many substantial contributions back into the Bookshelf • Software: New modifications to existing Bookshelf component • Applications (LEF/DEF): 1-D DCT, 2-D DCT, 1-Round IDEA encryption • Likely future additions: AES, FFT, Low-Density Parity Check, …

19. One-Round IDEA Encryption Benchmark • Hold area used to fix hold-time violations: 9.5% (No Floor) vs. 1.8% (New)

20. New Mindset: On-Demand, Pervasive Automation • Another “trivial” idea: Automate all design activities that cost time/$$$ • Bottom-up: “intelligent” solvers • Top-down: goal-driven, platform-based methodologies • Sideways: “intelligent” VLSI design environment • “We automate what you do” (if we can understand it ) • Fundamental techniques for automation (e.g., OO-based design patterns for EDA) • Generic, reusable, high-performance SW and HW components (e.g., Capo, PipeRench) • Common practices and methodologies for automation

21. “We Automate What You Do” • Goal: Reconfigurable and robust design flows • modular implementation platforms • language support for rapid flow prototyping • Web-based script composers for design flows • file-system support for distributed flows • design flow health monitoring • automatic extraction of statistically significant results • Additional motivations • Related research: PUNCH from Purdue, SatEx from CNRS/U. Paris-Sud (France), NEOS from Argonne National Lab, PBS from NASA, OmniFlow from NCSU/CBL • Benchmarking and regression testing • Experience in education: auto-graders (large-scale infrastructure for evaluation) • Experience with infrastructure for collaborative research (based on the Bookshelf )

22. bookshelf.exe • Best existing features • Reporting style of SatEx • Versatility of PUNCH • Scalability of NEOS • Control as in OmniFlow • New features • MIME-like data types • Flow scripting • Automatic submission of binaries and source code • Scalable: distributed computation, automated maintenance • “Adapts to users” • Multiple levels of expertise, commitment • Sharing of public data, protection of proprietary data • “Screen-saver” grid computation mode, cf. SETI@Home, Entropia, etc.

23. Usage and Data Models • Infrastructure proposal (IBM/Cadence, IWLS02): Study netlist changes for improved routing congestion • IWLS benchmark API • Interface to Bookshelf formats • Layout generation (in Bookshelf) • Placement (several in Bookshelf) • Congestion maps (in Bookshelf) • Consistent data models needed for serious flows, experimental research • E.g., integrated RTL-to-layout implementation, industry interoperability • Plan to use OpenAccess 2.0 (spec available 2Q02, source expected 1Q03) • Adjustments expected within Bookshelf for open-source / industry SP&R flows

24. Specific Projects (3) Design Process Optimization METRICS

25. T1 T2 T3 Tool Tool Flow Wrapper Transmitter Transmitter Java Applets API wrapper XML Inter/Intra-net Servlet Web Server Metrics Data Warehouse Reporting SQL Data Mining request Tables results DB Tables Tables Datamining Interface results SQL METRICS Architecture

26. Recent Progress • DAC-2002 Birds-of-a-Feather Meeting • 20 attendees (18 from industry, including HP, IBM, Intel, Motorola) • Industry adoption: • Cadence Design Systems • METRICS integrated into Block-Based Design Methodology for Front-End Acceptance, Clock Planning and flow quality tracking • Used within iCadence (web-based design flow) • Texas Instruments • METRICS used for flow/design quality tracking

27. Front End Acceptance Customer Data Validation Chip Design Planning Design Feasibility Assessment Verification Block Design Project Planning and Design Budgeting Chip Assembly Floor plan & Estimation Clock Bus Test AMS Power Timing Block-Based Design (BBD) Methodology Design Input Block Design Block-Based Design is a patented technology by Cadence Design Systems, Inc.

28. Clock Planning Methodology • Create IP clock reference library • store historical information on previous IP • Define basic clock speed • find master clock frequency that satisfies constraints for all blocks • Generate clock budgets • determine target gate count and target freq. to drive synthesis: • define insertion delays and skews from DB • Determine clock structures, variants • balanced buffered, grid, unbuffered H • Verify clock structures • timing correctness • adjust clock frequency, • padding, PLL taps, … H-tree Buffered Tree Delay Grid Loading Ref: K. Venkatramani, S. Mantik and R. Adhikary, “A Predictive and Analytical Clock Planning Methodology for Hierarchical Block Based Design”, DATE-2002

29. FEA Preparation Customer Data & Specifications Customer Data Validation Design Feasibility Assessment No Renegotiate Specification or Terminate Project Yes Project Planning and Design Budgeting Design and Project Data To Chip Planning and Block Design Meet Requirements? Front End Acceptance (FEA) Flow • FEA preparation • data gathering, classification and certification • Customer data validation • project checklist (docs, specs, testbenches, models, etc.) • data completeness (readability, execution readiness, etc.) • simulations (block interconnect, chip-level functional model) • primary block selection • project directory structure • Design feasibility assessment • analysis of proposed design to determine acceptance risks • assess key project parameters (cost, area, performance, power) • Project planning and design budgeting • Project schedule, human/machine resources, cost/expense, etc. Ref: K. Venkatramani and S. Mantik, “Managing Risk in Block Based Designs: A Front End Acceptance Methodology”, EDP-2002

30. METRICS Impact at Cadence • Clock Planning and Front-End Acceptance • METRICS used as design data (IP) repository • Clock planning applied to a wireless modem design consisting of 8 main IP blocks (total of 1M cells) achieves 54MHz speed on ARM architecture • FEA achieves more accurate coarse-grain assessment, reducing design risk without sacrificing design time • Flow quality tracking • METRICS keeps track of design quality and timing in a web-based SP&R flow for timing convergence

31. C.A.D. Theme Deliverables • Most C.A.D. Theme research is available as open source • Integrated as GTX models • Research at UCSC, UCB, CMU, Michigan all captured and interoperable • GTX is also available with the ITRS-2001 release (SEMATECH website) • Released in the GSRC Bookshelf • Many point optimization codes; CMU libraries and reference designs • Released in the METRICS system • Our open source is really open source • MIT license; can be used for ANY purpose (many positive comments from major companies such as Intel, IBM) • 60+ publications also posted on GSRC website

32. Roadmap and Collaboration GTX + Living ITRS: What is the design problem? Identify missing components / emerging challenges (mixed signal, reliability) GTX + Living ITRS: What is the design problem? Develop solutions for emerging problems • Select Design Drivers: • Ambient intelligence • In-home networks • Radar-on-a-chip Bookshelf, METRICS Develop prototype platforms (architecture, implementation) that meet design driver needs Identified challenges and issues in UDSM design Collaborate with C2S2 FCRP SRC (?) & Sponsors Joint project between themes to develop prototype implementation Formulated validation problem for PBD Developed Concept of Platform- Based Design (PBD) Develop and integrate associated tools and methodologies (capture, synthesis, optimization, verification, test) Developed and published taxonomy for PBD Refine and transfer methodology Explored potential methodology solutions Bookshelf, METRICS and bookshelf.exe bookshelf.exe (auto-flow opt) Explored and developed underlying tools and methodologies Bookshelf, METRICS and bookshelf.exe (design process opt) Jan 2005 Interfaces to other FRCs: GTX + Living ITRS, Cost modeling Today Jan 2003 Jan 2004 Jan 1999 Other interfaces to SRC and Sponsors: Education, Living ITRS “Shared Red Bricks”