1 / 36

Anatomy of a Computer: What Computers Can and Cannot Do

This article explores the capabilities and limitations of computers, including the deterministic nature of instruction execution, the fetch/execute cycle, and the principal subsystems of a computer. It also covers memory, control unit, arithmetic/logic unit (ALU), input and output units, peripherals, storage devices, device drivers, and the fetch/execute cycle.

charlsie
Download Presentation

Anatomy of a Computer: What Computers Can and Cannot Do

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. What Computers Can and Cannot Do • Computers deterministically perform instructions • No creativity, intuition, etc.

  2. The Fetch/Execute Cycle • “Instruction Execution Engine” • Fetch/Execute Cycle • Fetch next instruction • Decode • Gather needed data • Perform op • Save result • Repeat

  3. A Five-Step Cycle • Ops repeat forever

  4. Anatomy of a Computer • All computers have • Memory, • Control unit, • Arithmetic/logic unit (ALU), • Input unit, and • Output unit

  5. Principal Subsystems of a Computer

  6. 1. Memory • Memory • Code and data • Sequence of cells to hold bytes

  7. 1. Memory • Addresses • 0 to 232 – 1 (32-bit CPU) • Values • 8-bit • Finite capacity

  8. Byte-Size Memory Location • Discrete locations are shown as 1B boxes

  9. Byte-Size Memory Location • Location can store 8-bits • ASCII character • Number (how big?) • Block of four bytes is word

  10. Random Access Memory • Random access memory (RAM) • Order and time of access • Measured in MB or GB

  11. 2. Control Unit • Control unit • Circuitry handles Fetch/Execute Cycle • Typical machine instruction ADD 4000, 2000, 2080

  12. 2. Control Unit • ADD 4000, 2000, 2080 • Sums all three #s? • OP Dest, Src1, Src2

  13. Illustration of a single instruction

  14. 3. Arithmetic/Logic Unit (ALU) • ALU does math • Uses logic gates (AND, OR, NOT) • +, -, *, /, etc.

  15. 4. And 5. Input and Output Units • Input • Info => computer • Output • Info => User • Useless without

  16. The Peripherals • Peripherals connect to I/O ports • Not considered part of computer • Encode or decode info b/w computer and physical world

  17. The Peripherals • Keyboard • Encodes keystrokes • Monitor • Decodes memory • Peripherals handle physical part of operation

  18. Portable Memory & Hard Drives • Storage peripherals can do both I/O • USB memory • Hard disks/drives

  19. Hard Disk • Hard disk stores programs and data • Large capacity relative to RAM • Slow relative to RAM • Programs/data must reside in RAM for use

  20. A Device Driver for Every Peripheral • Most peripheral devices are “dumb” • Need drivers • Video card, monitor • Printer • Mouse, keyboard

  21. The Program Counter:The PC's PC • Program counter (PC) • Maintains address of next instr. • Instr Fetch (IF) • Instr. = MEM[PC] • PC = PC + 4

  22. Branch and Jump Instructions • Next instr. may not come after previous • Instr. may change PC • Jump • Branch

  23. Instruction Interpretation • Process of executing a program is instruction interpretation • Our language => computer language

  24. The Fetch/Execute Cycle • A five-step cycle: • Instruction Fetch (IF) • Instruction Decode (ID) • Data Fetch (DF) / Operand Fetch (OF) • Instruction Execution (EX) • Result Return (RR) / Write Result (WR) / Store (ST)

  25. ADD 800, 428, 884

  26. Instruction Fetch (IF) • Instr = MEM[PC] • PC is 2200 • Control Unit (CU) holds instr. • Bits of instr are decoded • PC updated

  27. IF ADD 800, 428, 884

  28. Instruction Decode (ID) • Decoder • Determines op to perform • Sets up ALU • Determines operand addresses • Sources • Destination • Passes to data fetch stage

  29. ID + ADD 800 428 884

  30. Data Fetch (DF) • Read data from memory • SRC1 = MEM[SRC_ADDR1] • SRC2 = MEM[SRC_ADDR2]

  31. DF 42 12

  32. Instruction Execution (EX) • Performs op indicated by ID • RES = SRC1OP SRC2 • Result held in ALU

  33. EX 54

  34. WriteResult (WR) • Writes result to memory • MEM[DST_ADDR] = RES • Cycle begins again

  35. RR 54

More Related