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Test Circuit for Locating Open Leads of QFP ICs

Test Circuit for Locating Open Leads of QFP ICs. M.Hashizume, A.Shimoura, M.Ichimiya, H.Yotsuyanagi The Univ. of Tokushima, JAPAN. Outline. Background Our targeted problem: =open lead location of CMOS QFP ICs Our test method Our test circuit and the design method

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Test Circuit for Locating Open Leads of QFP ICs

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  1. Test Circuit for Locating Open Leads of QFP ICs M.Hashizume, A.Shimoura, M.Ichimiya, H.Yotsuyanagi The Univ. of Tokushima, JAPAN

  2. Outline • Background • Our targeted problem:=open lead location of CMOS QFP ICs • Our test method • Our test circuit and the design method • Feasibility of test circuit design • Conclusion

  3. Background • Many logic circuits are implemented with fine-pitch QFP ICs and a PCB of fine line layout. (ex.)circuits that downsizing and high performance are not requested strongly • Open leads of QFP ICs occur more frequently in soldering process. [Targeted Defects] Open lead of QFP ICs occurring in soldering process Now, 0.4mm solder bridging pattern short open lead peeling-off pattern

  4. Our Targeted Problem • Our targeted tests: Tests in subcontract soldering factories • CUTs: circuit s made of QFP ICs in which downsizing and high performance are not requested strongly • Difficulty: • Boundary scan technology may not be introduced in QFP ICs. • Test vectors are provided from ordering manufactures and can not be generated in the factories, since detailed information for test generation is not supplied. • Soldering process should be optimized for each kinds of circuits. [Requirements] • powerful and expensive testers • test vectors and/or test generation for locating open leads Development of vectorless test method for locating open leads

  5. Test Method Proposed in BTW’07 • Test based on supply current of our test circuit • Test process: [1]Attach a test probe to the top of a targeted input lead [2]Provide AC signal [3]Measure iDDT(t) [4]If Eq.(1) is satisfied, an open occurs at the targeted input lead. iDDT(t)≥Ith (1) (rms)Open at an output lead is detected as open at an input lead.

  6. nMOS:off pMOS:off VDD IDD Vo Vo IDD IDD Vi Vo Vi1 Vi2 Vth Property Used in Our Test • If either Vi=VDD or Vi=0V, IDD=0 • If Vi1<Vi<Vi2, large supply current flows into a CMOS INV ICs. (a)Measurement Circuit Vi (b)DC characteristics

  7. Principle of Open Lead Detection • When an open occurs at an input lead, vINV(t) will depend on vs(t). • When Vi1<vINV(t)<Vi2, elevated iDDT(t) will flow. (a)Test of open lead (b)iDDT(t) waveforms

  8. (b)when H is outputted (a)when L is outputted Tests of Defect-free Circuits • vINV(t) depends on output voltage from IC#i-1 and iDDT(t) ≈0. If either H or L is outputted to a targeted lead, the lead will be judged as defect-free.

  9. Test Circuits for Detecting Opens in BTW’07 • Purpose: detect more than one lead simultaneously (a)Test circuit for locating open (b)Test circuit for detecting open

  10. Necessity of RT • If a CUT is defect-free, elevated iDDT(t) may flow and the CUT may be destroyed when H and L are outputted. RT’s make this current small. [Our new approach] This circuit is used for locating open leads.

  11. Drawback of Our Test Circuit in BTW’07 • When high-Z is outputted to a targeted lead in a defect-free circuit, the lead will be judged as defective.= Test vector generation and application are indispensable. Elevated iDDT flows. highZ (b)when open lead occurs (a)when high-Z is outputted

  12. Our Purposes • Revise test circuit proposed in BTW’07 so that expected test results can be derived even if high-Z is outputted. • Develop test circuit design method for locating open leads Pull-up circuits are added revised (b)Revised test circuit (a)Test circuit in BTW’07

  13. ON Our New Test Method • Principle: Tests with high-Z output leads pulled-up(ex.)Lead c is pulled-up by Sel2=H • Test process: • Test stage #1: Purpose: Locate leads of high-Z signal and open leads • Test stage #2:Purpose: Locate open leads from leads derived in Test stage#1 Pull-up circuits L H ≈0 L

  14. Test Stage#1 • Purpose: locate open leads and high-Z ones • Test procedure: [1]All of the targeted leads are pulled-up (Sel1,Sel2,Sel3)=(H,H,H) [2]For each of targeted leads, • Pull-up switch of i-th lead is turned off by Sel#i=L. • If iDDT(t)≥Ith, Sel#i=H. (ex.) Example of tests Results: (Sel1,Sel2,Sel3)=(L,H,L)

  15. Test Stage#2 Test Stage#2 Test Stage#1 • Purpose:Locate open leads by attaching a pull-up circuit to the input leads of targeted ones • Test Procedure: [1]Pull-up circuit is attached to targeted leads [2]For each of leads of Sel#i=H, • pull-up switch of only the i-th lead is turned off by Sel#i=L. • if iDDT(t)≥Ith, it is determined that open lead occurs at the i-th lead and Sel#i=H. (ex.) (Sel1,Sel2,Sel3)=(L,H,L) Even if high-Z signals are outputted, defect-free circuits will be judged as defect- free by attaching the pull-up circuit. L H→L L off ON off off H H Z H L L

  16. ON ON Example of Open Lead Location Test Stage#2 Test Stage#1 It can be judged what leads are opened even if high-Z signals are outputted. L →L→L L H→L →H H H off H→H→L on off H H Z H (a) test stage#1 L ?? (b) test stage#2

  17. Test Circuit Design • Goal: specify RT for defect-free circuits to be judged as defect-free. pull-up circuit for H output m-parallel L off L off n-parallel pull-down circuit for L output (b)Equivalent circuit H L (a)Test circuit in test stage#1 # of H output leads =m # of L output leads = n (c)Equivalent circuit of (b)

  18. vS(t) [V] vINVH(t) Vi2 min(vINVH(t)) vINVH(t),vINVL(t) [V] Vi1 vINVL(t) max(vINVL(t)) Conditions to be Satisfied • Conditions for defect-free circuits to be judged as defect-free: • min(vINVH(t))>Vi2 (2) • max(vINVL(t))<Vi1 (3) (b)Input voltage of INVs in defect-free circuit tests (a)Equivalent circuit

  19. nMOS:off pMOS:off Vo Vo IDD IDD Vi1 Vi2 Vth Test Circuit Design • Test circuit design for N(=m+n) leads m: # of H outputted leads n: # of L outputted leads VDD IDD worst-case design for m=N-1,n=1 Vi Vo for m=1,n=N-1 (a)Measurement Circuit where (b)DC characteristics

  20. Experimental Evaluation • Purpose: Examine feasibility of our test circuit design • CUT: # of leads =50 [Specifications] • VDD=5.0, Vi1=0.8, Vi2=4.2, Rpon=2.3k, Rnon=3.0k from IC#i-1 • Vs=VDD/2=2.5, Rs=100 • Derivation of RT • RT≥9.3k from min(vINVH)>Vi1, • RT≥23.5k from max(vINVL)<Vi2 RT=26k

  21. Evaluation Results • Evaluation by Spice simulation with RT=26k VSD: Voltage of open lead (a)defect-free circuit (b)circuit having an open lead Expected test results are obtained with the test circuit designed by our design method.

  22. Conclusion • A new test circuit for locating open leads of CMOS QFP ICs [features] • Simple test circuit • Vectorless test method Open leads can be located in subcontract soldering factories. • Test circuit design method [Evaluation by SPICE simulation] • 50 leads are tested with the test circuit designed by our design method successfully. • Development of test probes • Open lead location in real ICs with our test circuit Future works

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