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Adding the TSE component to BANSMOM system and Software Development

Adding the TSE component to BANSMOM system and Software Development. m 5151117 Yumiko Kimezawa. Outline. Previous Work Implementing a Triple-Speed Ethernet (TSE) component (Hardware) Current Work Adding the TSE component to BANSMOM system Software Development (unfinished) Future Work.

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Adding the TSE component to BANSMOM system and Software Development

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  1. RPS Adding the TSE component to BANSMOM system and Software Development m5151117 Yumiko Kimezawa

  2. Outline RPS • Previous Work • Implementing a Triple-Speed Ethernet (TSE) component (Hardware) • Current Work • Adding the TSE component to BANSMOM system • Software Development (unfinished) • Future Work

  3. Triple-Speed Ethernet (TSE) part RPS • Components • Triple-Speed Ethernet • TX SDGMA • RX SGDMA dispensable User Interface Host PC Stratix III Transfer ? Receive

  4. Optimized HW RPS • Block diagram of optimized hardware : Data flow : Control signal 1: Signal Reading Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

  5. Optimized HW RPS • Block diagram of optimized hardware 2: Filtering : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

  6. Optimized HW RPS • Block diagram of optimized hardware : Data flow : Control signal 3: Processing Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

  7. Optimized HW RPS 4: Display & Transferring data • Block diagram of optimized hardware : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

  8. Software Development RPS • Creating a NicheStack TCP/IP stack and MicroC-OS/II • Now, I am investigating

  9. Software Architecture Model RPS • The onion diagram shows the architectural layers of a Nios II MicroC/OS-II software application Application Application-specific system initialization NicheStack TCP/IP Stack software component Software Micro C/OS - II HAL API Software device driver Nios II Processor system hardware Hardware

  10. Future Work RPS • Investigating NicheStack TCP/IP stack and MicroC-OS/II to get data from shared memory and send it to the host PC

  11. RPS

  12. Optimized HW (Proposal) RPS : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

  13. Optimized HW (Proposal) RPS : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

  14. Optimized HW (Proposal) RPS : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

  15. Optimized HW (Proposal) RPS • Block diagram of optimized hardware : Data flow : Control signal Ethernet PHY JTAG UART LED Graphic LCD FPGA Graphic LCD Controller PPD CPU PPD CPU Memory LED Controller External Memory Raw ECG data TSE MAC Avalon Bus TX SGDMA Shared Memory Timer Master CPU Master CPU Memory FIR Filter Timer PPD Module Ethernet Master Module

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