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Barriers: Friend or Foe?

Barriers: Friend or Foe?. Steve Blackburn Department of Computer Science Australian National University. Tony Hosking Department of Computer Sciences Purdue University. Read & Write Barrier Costs. Are r/w barrier costs significant?. Read and Write Barriers.

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Barriers: Friend or Foe?

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  1. Barriers: Friend or Foe? Steve Blackburn Department of Computer Science Australian National University Tony Hosking Department of Computer Sciences Purdue University International Symposium on Memory Management Vancouver BC, October 2004

  2. Read & Write Barrier Costs Are r/w barrier costs significant? International Symposium on Memory Management Vancouver BC, October 2004

  3. Read and Write Barriers • Algorithmically powerful mechanisms • Extend semantics of each read/write • Particularly useful to GC • Untested assumption: “read/write barriers are expensive” • Curtails creativity in GC algorithm development • Encourages (unnecessary?) work on avoidance • Prior work • [Zorn 1990] (used simulation & traces) • [Blackburn & McKinley 2002] (compilation & inlining) International Symposium on Memory Management Vancouver BC, October 2004

  4. Our Contributions • Methodology for measurement • Evaluate mutator overhead • 5 common w/b, 2 r/b • 9 benchmarks • 3 architectures (AMD, P4, PPC) • Exclude compiler, GC from measurements International Symposium on Memory Management Vancouver BC, October 2004

  5. Methodology • Want to remove barrier • Compare with and without barrier • Add full trace to generational collector • Remembered objects irrelevant • Can include/exclude barrier • MMTk, Jikes RVM • Hardware performance counters • Pseudo-adaptive (realistic, deterministic) • Second iteration (avoid compiler overhead) • Best of 5 (least disturbed) International Symposium on Memory Management Vancouver BC, October 2004

  6. Write Barrier Code 1 publicfinalvoid writeBarrier(ObjectReference src, Address slot, ObjectReference tgt, int mode) throws InlinePragma { // insert write barrier code here slot.store (tgt); } International Symposium on Memory Management Vancouver BC, October 2004

  7. Write Barrier Code cont. International Symposium on Memory Management Vancouver BC, October 2004

  8. Experiments: Hardware • 3 platforms: • 1.9GHz AMD Athlon XP 2600 1GB • 2.6GHz Pentium 4 1GB • 1.6GHz PowerPC 970 768MB • AMD and Intel performance counters • cycles • instructions retired • L1/L2 cache misses • TLB misses • both mutator and collector, separately International Symposium on Memory Management Vancouver BC, October 2004

  9. Experiments: Software • MMTk in Jikes RVM version 2.3.2+CVS • ignore remsets GC configuration (now in MMTk) • patched to support performance counters • pseudo-adaptive compilation • read barriers • Debian Linux 2.6.0 kernel + x86 perfctr • Standalone mode International Symposium on Memory Management Vancouver BC, October 2004

  10. Write Barrier Overheadmean of SPECjvm98 & SPECjbb International Symposium on Memory Management Vancouver BC, October 2004

  11. Write Barrier Code (Again) International Symposium on Memory Management Vancouver BC, October 2004

  12. Write Barrier Code (Again) International Symposium on Memory Management Vancouver BC, October 2004

  13. Write Barrier Code (Again) International Symposium on Memory Management Vancouver BC, October 2004

  14. AMD Athlon 2600+ 1.9GHzWrite Barrier International Symposium on Memory Management Vancouver BC, October 2004

  15. Intel P4 2.6GHzWrite Barrier International Symposium on Memory Management Vancouver BC, October 2004

  16. G5 PowerPC 970 1.6GHz Write Barrier International Symposium on Memory Management Vancouver BC, October 2004

  17. Performance Counters International Symposium on Memory Management Vancouver BC, October 2004

  18. Intel P4 2.6GHzWrite Barrier Retired Instructions International Symposium on Memory Management Vancouver BC, October 2004

  19. Intel P4 2.6GHzWrite Barrier L1 Misses International Symposium on Memory Management Vancouver BC, October 2004

  20. Intel P4 2.6GHzWrite Barrier L2 Misses International Symposium on Memory Management Vancouver BC, October 2004

  21. Intel P4 2.6GHzWrite Barrier DTLB Misses International Symposium on Memory Management Vancouver BC, October 2004

  22. Read Barrier Code 1 public final ObjectReference readBarrier(ObjectReference obj, Address slot, int mode) throws InlinePragma { ObjectReference value = slot.loadObjectReference(); return value; // insert read barrier code here } International Symposium on Memory Management Vancouver BC, October 2004

  23. Read Barrier Code cont. International Symposium on Memory Management Vancouver BC, October 2004

  24. Read Barrier Overheadmean of SPECjvm98 & SPECjbb International Symposium on Memory Management Vancouver BC, October 2004

  25. AMD Athlon 2600+ 1.9GHz Read Barrier International Symposium on Memory Management Vancouver BC, October 2004

  26. Intel P4 2.6GHzRead Barrier International Symposium on Memory Management Vancouver BC, October 2004

  27. G5 PowerPC 970 1.6GHz Read Barrier International Symposium on Memory Management Vancouver BC, October 2004

  28. Conclusions • New methodology: available in MMTk • Specific barrier patches at: http://cs.anu.edu.au/~Steve.Blackburn/pubs/wb-ismm-2004.tgz • Barrier costs (often) surprisingly low • Barrier costs very architecturally sensitive • GC developers: think about your target arch. • GC papers: what architecture did they use? • Architects: choices impact OO languages in surprising ways. International Symposium on Memory Management Vancouver BC, October 2004

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