Fundamentals of Digital Logic

1. Fundamentals of Digital Logic B. Furman 25NOV2014

2. PowerSource SignalConditioning PowerInterface Sensor System toControl ME 110 ME 136 ME 154 ME 157 ME 182 ME 189 ME 195 Mechatronics Concept Map ME 106 ME 120 UserInterface EE 118 Controller(Hardware & Software) ME 106 ME 190 ME 187 ME 106 INTEGRATION ME 106 ME 120 Actuator ME 106 ME 154 ME 157 ME 195 ME 120 ME 297A BJ Furman 26JAN06

3. Digital Logic • Combinatorial Logic • The combination of logic states (0’s and 1’s) at the inputs of logic gates (digital logic elements) determines the output state according to the logic function. • AND, OR, NOT, XOR • NAND, NOR • Ex. 7447 BCD-to-7-segment decoder; ‘enable’ inputs • Sequential Logic • The combination of input logic states and their sequencing determines the output state • Flip-flops • Ex. Computer memory, microcontroller registers

4. Review of Logic Functions • AND, OR, NOT, XOR, NAND, NOR

5. Truth Tables for Logic Functions

6. Boolean Algebra Laws and Identities • See the handout

7. All logic functions can be formed from NAND or NOR gates alone

8. Demorgan’s Theorem • You can swap shapes (AND or OR), if at the same time you invert all inputs and outputs.

9. Z Combinatorial Logic • The three logic functions, AND, OR, and NOT can be used to build any digital device • NAND gates or NOR gates are universal, i.e., can be used to construct the three logic functions, hence any digital device • Ex. A

10. Internal Construction – Inverter (TTL) A Z input output (Source: http://www.allaboutcircuits.com/vol_4/chpt_3/2.html)

11. Input High (1) Input Low (0) 5 V 0 V Inverter Operation (Source: http://www.allaboutcircuits.com/vol_4/chpt_3/2.html)

12. CMOS Inverter http://www.allaboutcircuits.com/vol_4/chpt_3/7.html

13. Logic Chips - c. 1960’s and 1970’s • Multi-input versions exist • Examples: • 7421 Dual 4-input AND • 74LS00 Quad 2-input NAND http://www.oup.com/us/pdf/microcircuits/students/logic/74LS00-motorola.pdf

14. Logic Chips c. 1980 – pres. • Programmable logic devices (PLD) • Programmable Array Logic (PAL) • Generic Array Logic (GAL) • Lattice Semiconductor c. 1985 • Erasable and reprogrammablePAL device • Complex Programmable Logic Device (CPLD) • More gates than PALs and GALS • Field Programmable Gate Array (FPGA) http://www.xess.com/appnotes/fpga_tut.php

15. Field Programmable Gate Array (FPGA) • A ‘programmable’ digital logic device • You define the logic functions in a Hardware Descriptor Language (HDL) • Compile the HDL description into a binary file • Download the binary to the FPGA device • Voila! You have a device that will execute your logic function • For more information: • http://www.fpga4fun.com/index.html

16. Combinatorial Logic Circuit Design • Vote counting circuit

17. Digital Logic Families • See the handout

18. Sequential Logic • Output based on input values and their sequencing • timing is important! • Will often use trigger signals, called ‘clock’ (Clk) signals to trigger events • Flip-Flops(also known as bi-stables or latches) • Devices that can store and switch between binary states, 0 and 1 • Fundamental building block of all semiconductor memory and processing in digital computers • Made up of logic gates with feedback (some outputs are fed back to inputs of other gates)

19. S S Q Q R R 1 0 1 1 1 0 0 0 R-S Flip-Flop • S stand for ‘set’ • R stands for ‘reset’ • Q and Qbar are complementary outputs S tprop(inverter) tprop is the ‘propagation delay time’, which is the time it takes the logic gate to change its output state following a change in the state of the input. R tprop(NAND) Q tprop(NAND) NA means ‘not allowed’ Time

20. S Q Clk R Triggering Flip-Flops • Often important to synchronize changes on a clock signal • Types of clock signals to trigger on: • Level(no ‘wedge’ symbol. If no bubble, active HIGH. With bubble, active LOW) • Negativeedge (bubble+wedge): 1  0 transition • Positiveedge (wedge): 0  1 transition Active-LOW (level triggered) R-S Flip-Flop Active-HIGH (level triggered) R-S Flip-Flop Negative Edge-Triggered R-S Flip-Flop NA means ‘not allowed’ means activated on rising edge of clock signal (positive edge)

21. Preset D Q Clk Clear Other Types of Flip-Flops - 1 Truth Table Ex. Positive edge-triggered D flip-flop • D Flip-Flop (ex. 7474) What are ‘preset’ and ‘clear’? Single input is stored and presented to Q on edge of clock pulse Preset pulled low (“active low”) will set Q to 1 Clear pulled low (“active low”) will clear or reset Q to 0 Scherz, Practical Electronics for Inventors, p. 688

22. Preset J Q Clk K Clear Other Types of Flip-Flops - 2 Truth Table • JK Flip-Flop (ex. 7476) Positive edge-triggered JK flip-flop Like RS flip-flop, where J is like S and K is like R, but can have both J and K high. This will cause output to toggle (change state) Scherz, Practical Electronics for Inventors, p. 692

23. Sequential Logic Applications - 1 Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2nd ed., McGraw-Hill, NY.

24. Sequential Logic Applications - 2 Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2nd ed., McGraw-Hill, NY.

25. Sequential Logic Applications - 3 Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2nd ed., McGraw-Hill, NY.

26. Sequential Logic Applications - 4 A ‘T’ flip-flop is essentially a JK flip-flop with J and K inputs tied HIGH and the clock input tied to the T input Figure from Alciatore, D. G., and Histand, M. B. Introduction to Mechatronics and Measurement Systems, 2nd ed., McGraw-Hill, NY.

27. 555 Timer IC • See handout • Uses a flip-flop • Many applications • Precision timing • Pulse generation • Sequential timing • Time delay generation • PWM http://www.doctronics.co.uk/pdf_files/555an.pdf http://www.555-timer-circuits.com/motor-pwm.html

28. 7447 BCD to 7-segment Decoder