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SVT. Layer0 update Open questions. Detector Session Elba SuperB Workshop May 31, 2010. Giuliana Rizzo Universita’ & INFN Pisa. Layer0 Update. Plan. Striplets baseline option for TDR:

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SVT

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  1. SVT Layer0 update Open questions Detector Session Elba SuperB Workshop May 31, 2010 Giuliana Rizzo Universita’ & INFN Pisa SVT – SuperB Workshop – Elba May 2010

  2. Layer0 Update Plan • Striplets baseline option for TDR: • Better physics performance (lower material ~0.5% vs 1% hybrid pixel, MAPS in between but not yet mature!) • Upgrade to pixel (Hybrid or CMOS MAPS), more robust against background, foreseen for a second generation of Layer0 • This study based on similar radius for various options (1.4-1.6 cm) • Radius & performance for the different technologies (striplets, thin pixel) depends on backgrounds rate! ~10% better ~20% more Luminosity SVT – SuperB Workshop – Elba May 2010

  3. Layer0 radius vs technology Update on background: • Hit rate vs Layer0 radius from pairs production depends strongly on sensor thickness: • on thick sensor larger cluster width for low momentum tracks with large crossing angle • Large difference for thin pixels (50 um) and striplets (200 um) • Hybrid pixel with 200 um sensor will be like striplets, unless thinner sensor can be used Sustainable background hit rate (radius) depends on technology: striplets vs pixel area and readout chip. • Development of thin pixel chip readout architecture continue: data push and triggered with target 100MHz/cm2 (safety x5 included) with timestamp 100 ns.  R~1.3cm • Still to demonstrate: scaling to large matrix, rad hardness for MAPS, • Assumed 100MHz/cm2 hard limit for striplets (~ 10% occupancy in 100 ns, area~10-2 cm-2)  R~2 cm • performance similar to BaBar and thin pixel at lower radius. No margin left! • BUT need a readout chip for striplets fast enough for this rate (next slide) SVT – SuperB Workshop – Elba May 2010

  4. FSSR2 chip for striplets/strips • Evaluate efficiency of FSSR2 readout chip (striplets) vs rate (goal still 100MHz/cm2): • Verilog simulation results not very encouraging! Significant drop in efficiency with hit rate ~20 MHz/cm2. • Need to interact with Fermilab designers to understand if this is a real issue and in case if modification to digital part are possible. • Started to investigate alternative option for striplets readout chip. • Shadowing effect due to analog response cause inefficiency: • channel dead time ~ 4xshaping time  Effi= 1/(1+Occu) ~ 90% with 25 ns. • Evaluate readout needs for the external layers: • long shaping time ~1 us needed to get reasonable S/N. • FSSR2 can be modified but with the data push architecture implemented the time window needs to be > 1 us (problems with background tracks) • Started to investigate alternative options for long strip readout chip. Probably need to have triggered architecture. • Readout chip for striplets/strips is a critical issue for TDR • By September clear picture of existing chips. • Difficult to have the same chip for striplets and long strip layers • If need to design new chips involvement of new groups mandatory SVT – SuperB Workshop – Elba May 2010

  5. TDR – SVT Baseline • Layer0 with striplets (technology mature but need some work): • Readout chip!. • Module assembly with multilayer fanout (still uncovered !) • HDI/transition card electronics (partly covered by M.Citterio assuming similar to pixel option…not enough!) • Layer1-5 strip detector: • Readout chip evaluation: • Module components: Si sensor/fanout/HDI • some manpower available in TS not enough! • SVT Mechanics: • Only 1 eng. available F.Bosi !!! • Very difficult to get new people involved without project approval! SVT – SuperB Workshop – Elba May 2010

  6. TDR – SVT Upgrade Options • Pixel/new technology: more appealing manpower less critical. Synergy with R&D projects (not SuperB specific). • Describe the upgrade path for Layer0: • Status of the R&D on hybrid pixel and CMOS MAPS. • Plan for Hybrid Pixel quite clear • FE chip tested. Interconnection with sensor matrix during the summer  Lab test in Autumn. • CMOS MAPS: • Proceed with the R&D (VIPIX Italian Collaboration): • Vertically integrated MAPS with 2 CMOS layers: • First chips should be ready by this summer (long delay in the production) • Next submission in October 2010 (results available for TDR?) • Layer0 mechanics well advanced. SVT – SuperB Workshop – Elba May 2010

  7. TDR preparation • Full technical details needed for baseline: • Layer0 with striplets (critical item the readout chip!) • Layer1-5 strip detector (readout chip for long strip modules is an issue- mech. and electr. eng. are missing!) • Describe the upgrade path for Layer0: • Status of the R&D on hybrid pixel and CMOS MAPS. • Depending on the evolution of the UK proposal in the next months include the MAPS all-pixel SVT. SVT – SuperB Workshop – Elba May 2010

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  9. R&D on pixel options Hybrid pixel: • Prototype Front-end chip for hybrid pixel (32x128, 50 um pitch) tested • Results in fair agreement with simulation • Pixel sensor matrix produced and tested: good quality • FE chip + sensor matrix bump-bonding in june and test in lab in September CMOS MAPS: • Pixel readout architecture for next matrix (3D MAPS with 2 CMOS layers interconnected, ~Dec 2010) could work in data push and triggered mode • triggered readout reduces pixel module complexity (lower speed for links & less material for pixel bus) • Better definition of the pixel module interfaces. SVT – SuperB Workshop – Elba May 2010

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