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SVT upgrade

AM 32kpat  128kpat Road Warrior. SVT upgrade. SVT upgrade: E’ parte dei DAQ upgrades per aumentare “Trigger bandwidths” Tracce SVX only per migliorare il trigger di leptone inclusivo DAQ upgrades a CDF: 6 M$ Chi saremo – Schedule. Paola Giannetti – Gruppo I Lecce - 24 settembre 2003.

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SVT upgrade

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  1. AM 32kpat  128kpat Road Warrior SVT upgrade • SVT upgrade: • E’ parte dei DAQ upgrades per aumentare “Trigger bandwidths” • Tracce SVX only per migliorare il trigger di leptone inclusivo • DAQ upgrades a CDF: 6 M$ • Chi saremo – Schedule Paola Giannetti – Gruppo I Lecce - 24 settembre 2003

  2. SVT: Silicon Vertex Trigger XFT + SVX 4/4 (fino a 6/2003) XFT + SVX 4/5, more efficient Instead of XFT: • m 1<h<1.5 e 1<h<2.5 New Functionalities: m + SVX 4/5,1< h< 1.5 e + SVX 4/5, 1< h< 2.5 XFT tracks SVX hits

  3. I limiti ai rate dei tre livelli di trigger XFT (2227 k$) L2 (429 k$) SRC (Done) SVT (? K$) upgrade 350 Hz (L3-EVB) TDC (2132 k$) EVB (680 k$) L3 (631 k$) upgrade 15 kHz (L2 proc. Time) L1 Accept rate (Hz) L2 Accept rate (Hz) Time (sec) CSL (?k$) Offline (1M$) upgrade 70-80 Hz (L3-CSL) Dead Time L3 Accept rate 5% Time (sec)

  4. Accurate deadtime model (ModSim) to understand DAQ upgrades M. Schmidt • Two SRCs in parallel • L2 processor upgrade • 87 bit SVX digit. • -3 ms in SVT proc.time • cut SVT tails above 27 msec 4/4 DeadTime 20 kHz BUT the recent use of 4/5 in SVT changes the conditions! 5% 35 kHz L1A rate (kHz) 4/4 – 4/5 25 kHz • match piu’ debole • Ghost roads • 5 layers: Pattern + larghi 4/4 – 4/5 27 msec Time (ms)

  5. WHY 4/5? Signal Yields with 4/5 1430 D0 4/5 J/psi 970 D0 4/4 Marco RescignoCSL review 6/23/03

  6. Signal Yields in 4/5 Several studies: • D0 peaks in RUN 164303 (4/4) and 164304 (4/5) (Rolf) • EXPRESS_JPSI stream for 4/5 runs with svtsim emulation of 4/4 to get directly the yield increase of J/psi with both legs an SVT track • BGEN MC with realistic simulation of BsDsp(fp) p • Increase in signal yield match almost exactly the increase in L3 yield: S/B unchanged GAIN 50-60 % Marco RescignoCSL review 6/23/03

  7. NUOVA AM piu’ grande Hit Finders raw data from SVX front end Sequencer Associative Memory COT tracks fromXTRP x 12 phi sectors roads Road Warrior 12 fibers hits Track Fitter to Level 2 Merger hits Hit Buffer Tempi di processamento: come agisce l’upgrade? • Ricetta per velocizzare il tempo di esecuzione di SVT: • pattern piu’ sottili (AM grande)  menofits. • Road Warrior per rimuovere i ghosts

  8. 4/5 – 128kp – RW – All Annovi/Belforte Gli upgrade riportano la distribuzione dei tempi del 4/5 su quella del 4/4 ! 4/5 – upgraded 4/5 – 4/4 Detector Ghosts XFT svx

  9. SVT ha recentemente attivato il 4/5. Complessita’ e tempo di esecuzione sono aumentati. 4/5 Detector ghost 4.3 14.5 ROAD WARRIOR e AM ++ riportano il tempo di esecuzione a quello del 4/4 !

  10. Accurate deadtime model (ModSim) M. Schmidt 4/5+SVTupgrade  4/4 4/5+SVTupgrade+L2upgrade 4/5 now Ini_lum=44*1030 3 4/4 16 Ini_lum=32*1030 Ini_lum= 17.5 *1030 Ini_lum=22*1030 17kHz

  11. BMU Trigger di muoni in avanti (Annovi - Catastini – Cerri) 1<<1.25 (FRONT) L1 ora: BMU*BSU(F)*XFT11 rate 8-16Hz @ 4E31 L2: RateLimited @ 0.7 Hz 1.25<<1.5 (REAR) L1 ora: BMU*BSU(R)*TSU Rate 200-400Hz @ 4E31 L2: RateLimited @ 1.3 Hz 1<<1.25BSU(F) 1.25<<1.5 BSU(R) SVX TSU • Usiamo SVT*BMU*BSU per un unico trigger, senza bias in  ! Goal reiezione ~ 20-50. • leptoniprontidi alto Pt solo 30kpatterns 95% efficiente per Pt>8 GeV e d0<500m (ottima efficienza fino a 4 GeV). Implementiamo il 4/5.

  12. STUDIO del NUOVO TRIGGER • Qualita’ delle tracce SVX only: studio su dati e MC • Efficienza selezione L2: studio tagli su dati Z0 mm • Regezione del fondo: studio su dati selezionati da L1 ora

  13. J/Psi: MC vs SVT SVT: 2<10; |MCf0 – SVTf0|< 0.015 s(f)=0.007 sPt/Pt2=0.08 MCf-SVTf MCPt-SVTPt MCCRV-SVTCRV QUALITA’ delle tracce SVX only? Limit: s(f) = 0.002, sPt/Pt2 = 0.07 L1_MU data: offline vs SVT SVT 2<10; |offlf0 – SVTf0|<0.015 f(SVT)- f(offl) s(f)=0.008 f match h match Pt match f effic. h effic. Pt effic, sPt/Pt2=0.095 60% 60% 60% c(SVT)- c(offl)

  14. f0 offl vs fBMU fBMU–f0 offl (best) f0 SVT vs fBMU fBMU–f0 SVT (best) • matching cut Scegliamo il trigger di livello 2: quali tagli? fBMU–f0 offl Z0-> data : Pt>4 & 2<10 Z0 eff ~ 50% f0 offl vs fBMU fBMU–f0 offl (best) fBMU–f0 SVT (best) f0 SVT vs fBMU 5o Pt>4 & 2<10+|fBMU–f0 SVT|< 5O CUT fBMU–f0 SVT L1 MU data Per stimare la reiezione Reiezione fondo ~ 22

  15. Conclusioni • L’upgrade di SVT permettera’ un raddoppio della banda passante di L1 ed e’ parte fondamentale del DAQ upgrade. • L’uso di tracce SVX only permette un trigger inclusivo di muoni in avanti e di abbassare le soglie di trigger per gli elettroni nel plug.

  16. Pisa: Annovi dottorando (100%) Bardi ingegnere - art. 23 (100%) Dell’Orso prof. Associato (100%) Giannetti dirigente di ricerca (100%) Spinella assegnista INFN (50%) Ferrara: Damiani assegnista (10%) Sartori assegnista (50%) Tripiccione prof. Ordinario (10%) Cotta tecnologo (10%) Chiozzi tecnico (20%) “A Standard Cell based Content-Addressable Memory System for Pattern Recognition” A. Cisternino et al., CERN/LHCC/98-36

  17. TEMPI DI REALIZZAZIONE • Nuova AM-board: inizio estate 2004 (Pisa) • durante estate 2004: test con FPGA (Pisa) • Progetto prototipo AM-chip: luglio 2004 (Ferrara-Pisa) • consegna chip ~2 mesi – disponibile ad ottobre. • Nuova LAMB: montare nuovo AM-chip a ottobre 2004 (Pisa) • test del chip + scheda: ottobre – dicembre 2004 (Pisa-Ferrara) • produzione: inizio 2005 (Pisa-Ferrara) • installazione: estate 2005 (Pisa-Ferrara) • Altri DAQ/Trigger upgrade: previsti nel 2006 RUN Multiprojects di Europractice: nel 2003 tutti i mesi eccetto luglio e Dicembre http://www.europractice.imec.be/europractice/ Road Warrior: fattibilita’in Pulsar  S. Belforte (~60 k$ Fermilab) messa in opera entro fine 2003  F. Spinella

  18. Backup slides SVT backup slides

  19. Il tempo morto (< 5%) genera limiti alla banda passante dei 3 livelli • ………………. • L1 accept rate of 30kHz appears to be achievable • Two SRCs, 7-bit digitization • SVT improvements • L2 upgrade • L2 peak rate limited by Event-builder • Current limit ~350 Hz • EVB group: 450 is possible- TDC improvements coming • Will keep up at high luminosity • Level 3 Limitations • Input: CPU power ….. • Output: Logging Rate…… J. Lewis CDF CSL Review 23 June 2003

  20. Level 1 @Lum=40x1030 cm-2 sec-1 • Two Major Components • Calorimeter Triggers: Jets, electrons, photons, etc.~4-5 kHz In SVT: L1_JET10_&_SET90 (Higgs multijet) L1_TWO_TRK2_&_TWO_CJET5 (Zbb) L1_MET15_&_TWO_TRK2 (Higgs Z  nn) ~2 kHz L1_TWO_TRK10_DPHI20 (Di TAU exotic) L1_EM8 (Gamma + bjet) L1_CEM4_PT4 (B electron) L1_CMUP6_PT4 (B muon) • Hadronic B Decays: Two XFT tracks~11-12 kHz • Using three classes of B triggers • Scenario A • pT>2, pT,1+pT,2>5.5, opp. charge, Df<135°; DPS for safety only • Scenario C • pT>2.5, pT,1+pT,2>6.5, opp. charge, Df<135°; NO DPS • Low PT • pT>2, Df<90°; Heavy DPS, saturate bandwidth • Not considered for long-term J. Lewis CDF CSL Review 23 June 2003

  21. Level 2 Predictions XFT (2227 k$) L2 (429 k$) SRC (Done) SVT (? K$) upgrade TDC (2132 k$) EVB (680 k$) L3 (631 k$) upgrade CSL Bandwidth: Aggressive Trigger Model To stay below 21Mb/s Some physics losses With baseline cuts, saturate bandwidth at ~7e31 if 30 kHz allowed @L1 CSL (?k$) Offline (1M$) upgrade J. Lewis CDF CSL Review 23 June 2003

  22. Year chip boards devel. Total • 2003? 120 kE 10 kE (test b.) 5 kE 135 kE • - 10 kE (protot.) 30 kE 40 kE • 53 kE 40 kE (produc.) 60 kE 153 k • Ferrara Pisa • Road Warrior e’ pagato da USA: sottratti i • 35 kE corrispondenti nel 2005 (grazie Stefano!)

  23. Level 2 Operation • Approximate Timing Diagram Ready to load next event

  24. 6 electrical barrels Z 3D info from SVT • Due categorie di tracce SVT: • (Dz=0) Tracce che entrano escono dallo stesso barrel • Tracce che attraversano i barrel. Conosciamo il sengo di . • Una traccia SVT corrisponde ad una • traccia offline se Dz=0 oppure se Dz • ha lo stesso segno di .

  25. BSU DT1< Thr. DT2< Thr. L1 Trigger: (DT1< Thr. ORDT2< Thr.) AND BSU Camere dei MU (BMU) + scintillatori esterni (BSU)

  26. Come migliorare il fattore di reiezione per il trigger di m Migliorabile con semplici accorgimenti aggiuntivi: • Uso dell’informazione di hadron timing • Riduzione della finestra temporale per gli scintillari BSU e TSU • Usare il beam constraint per il track fitter • Migliora la risoluzione in Pt • Riduce il numero delle tracce false

  27. Z0 TRIGGER STUDY

  28. 0.9 0.9 0.8 0.7 5 GeV Higgs bb (mass = 110 GeV) Z0 ha efficienze minori (mass = 90 GeV)

  29. RUN IB Minimum Bias events

  30. 4/5 4/5 4/5 5/5 4/5 This road share all hits with the 5/5. It’s a ghost. These 3 roads share all hits. Two are ghosts. NOW pattern recognition with 5 SVX layers uses larger patterns w.r.t. 4 SVX layers More fakeroads and more hits inside roads Solution: More AM  thinner patterns  reduce fakes Why 4/5 is more complex? Ghosts are 60-70% of 4/5 roads. Removing them speeds up 4/5 processing time.

  31. Sorgenti di inefficienzaper m da Z0

  32. Super Pattern Super Bin Full Resolution Hits Road Road use most significant bits only Tracking in 2 steps: find Roads, then findTracks inside Roads

  33. The Event The Pattern Bank ... TRACKING WITH PATTERN MATCHING The Associative Memory (AM) • Dedicated device-maximum parallelism: • each pattern has its private hardware to • compare with the event. • Roads search during detector readout Bingo scorecard

  34. SVX only c2 distribution

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