Case of smart camera system

1. Case of smart camera system Paul Brelet TRT paul.brelet@thalesgroup.com 24/11/2011 1

2. Introduction • Socket Flow. • Hardware Design Flow. • Tools: • SPEAR DE • MAGILLEM Tools • GAUT Workshop - November 2011 2

3. SoCKET Flow System Requirements System Properties Global SoC Req. Metrics Metrics SoC Architecture Traffic generator HLS Requirements traceability Hardware properties Software properties Platform Assembly Headers generation IP-XactSoC C/C++/ASM TLMLT Software Functionality Functional validation Instruction Set Simulator TLMAT Fonctionnalité +timing Software SW Performance Validation RTL Software HLS Co-simulation/Co-emulation Silicon Software 3 Execution

4. Phase 2: HW Design • Level: RTL. • Tools: - GAUT: Apply on accelerator engines. - Magillem: Packager, Platform Assembly, Generator Studio. - SPEAR DE: Mapping • Validation : Register Level. • Links : - Scripts « bash ». Workshop - November 2011 4

5. Thales Flow: RTL Validation Generator Studio Generic client TE SystemCSkeleton client GAUT IP-XACT library Template JET VHDL Acc. client PLT Assembly MDS MRV Generator Netlister MDS Vhdl Spear Application FPGA HAL 5 Validation

6. SPEAR Tool Workshop - November 2011 6

7. SPEAR: Application • Application catching Workshop - November 2011 7

8. SPEAR: Application • Change the I/O: Fitting/paving • Automatic cornerturn Workshop - November 2011 8

9. SPEAR: Architecture • Architecture Model Workshop - November 2011 9

10. Mapping SPEAR • Application mapping Workshop - November 2011 10

11. SPEAR: Code generation • Code generation Workshop - November 2011 11

12. TLM Simulation Workshop - November 2011 12

13. MAGILLEM Tool • RTL Level: - Bus interface, components creation, link between components: ditto TLM. • VHDL code generation: - Using generics. - The code is readable by an individual. - Inter-connects are taken into account during the VHDL code generation. Workshop - November 2011 13

14. GAUT Tool • The C code: - The C code must be very close to VHDL code. • Comparison with commercial tools: - Roccc, ImpulseC. • Some troubles during VHDL code generation: - The generated code can be synthesizable but it does not work well in placement/routing. Workshop - November 2011 14

15. IP-XACT Advantage • Standard: Reuse strategy • Support of SystemC Model by TLM ports • Opportunities for “bottom up” and “top down” • XML Transformation: correct and complete XML descriptions • Hardware description: lot of data for several components Workshop - November 2011 15

16. Questions? Workshop - November 2011 16