APSEL6D architecture Simulations and results

1. APSEL6D architecture Simulations and results F.M. Giorgi - 5/17/2009 VIPIX collaboration

2. Outline • Briefing on the simulated 6D architecture • Some simulation results (efficiencies, …) • A 2D simulation scan BCO vs RDclk • Working status • Summary APSEL6D architecture simulations

3. The Matrix 320x256 (40µm pitch) 80 80 80 80 256 4 independent Submatrix 4 horizontal parallel scan 80 x 256 pxl MP 2x8 pixels APSEL6D architecture simulations

4. Submatrix readout 80 256 Barrel & Sparsifier concept same as 4D Apsel4D APSEL6D architecture simulations

5. Ref. Gabrielli vipix/prin07 meeting Pavia Submatrix Scan Policy NOW SIMULATED Da simulare… APSEL6D architecture simulations

6. Zone sparsification • 256 pixel / Z = Total number of vertical zones. (Z= zone width in pixels) • Every HIT contains the information of a zone, not of a single pixel. •  The 4D sparsifiers, process 8 pixels at a time. The proposed sparsifiers for the 6D chip process Nzones at a time (N is up-limited by synthesis complexity). • HIT= (Zone address+ Zone pattern) • Time Stamp: since the hits are time sorted, the relative TS word is stored at the beginning of each hit seqence 80 pxl Sparsifiers 2nd layer Barrels Z pxl Z pxl Z pxl APSEL6D architecture simulations

7. SIMULATIONS: VHDL models of the 6D architecture • Free parameters: • number of, disposition, x-y dimension of the submatrix. • x-y dimension of the Macro Pixels • Zone width • Number of sparsifiers • Barrel’s depths • All the parameters are defined in a vhdl package • Sparsifier (100%) • Barrels (B2, B1) (100%) • Sweeper (time-stamp oriented sweeping) (100%) • Scan Buffer (TS+MP_frozen_pattern) (100%) • Concentrator (time sorting preserved) (100%) • Slow control (work started in parallel progress) 1st layer barrel (B1) Sub Matrix Latch_en Sweeper Scan Buffer TS + MP pattern 2nd layer barrels (B2) Concentrator Sparsifiers All the VHDL parameterized models realized are synthesizable APSEL6D architecturesimulations

8. SIMULATIONS: the infrastructure • VHDL model of real Sub-matrix for behavioral simulation. • 2D array of MP entities, each one with uniform random hit generation. User-defined generation time granularity. • NO pixel dead time taken into account. (pixel immediately reset after read) • VHDL test bench • No hold condition on B1  whole B1 throughput available. • Monitoring of the B1 status (max and average filling level) • Start of Scan (SOS) words integrity check (out of each B2 and out of B1) • Mean sweeping time monitor (for BC period comparison) • Efficiencies evaluation: • Already hit pixel efficiency: a hit is generated on an already fired, but not frozen, pixel. (part of the εLatch) • Frozen hit efficiency: a random hit occurs on a frozen MP (part of the εLatch ) • Readout efficiency @B2 : hits read out of B2 / frozen hits (part of the εATR) • Readout efficiency @B1 : hits read out of B1 / frozen hits (part of the εATR) • BC-lost efficiency: [1 – BC_lost /(BC_lost+SOS_read) ]. BC_lost = Scan Buffer overflow counter. (Fired MPs get frozen on next BC rising edge. It doesn’t imply a hit loss, but if at least 1 S.B. overflow is detected in a run, temporal accuracy halves down). SOS_read = start of scan words read out of B1. • File logs • Simulation runs e-log (each parameter, monitor flag, and evaluated value of a simulation run is stored here: http://www.bo.infn.it/~giorgif/objects/run_parameters.txt) (consider ‘core version 1.6’ or higher) • Frozen hit log (once a MP gets frozen, the fired pixels within are stored in absolute x-y format) • B2 Readout log (stores the hits read out from any of the B2 decoded in absolute x-y format) • B1 Readout log (stores the hits read out from B1 decoded in absolute x-y format) • Hit controller program: C++ tool to check the correspondence between frozen hits and hits read out of B1 APSEL6D architecturesimulations

9. Barrel efficiency Rate A Rate B B2 Rate B/ Rate A depth • Taking into account the previous simulation results (F.Giorgi – 4/3/09) • we used for this test campaign: • B2 depth = 8 • B1 depth = 32 Expected rate @B2: 8,2 MPxl/s Expected rate @B1: 32,8 MPxl/s APSEL6D architecture simulations

10. Some interesting simulation results of the submatrix(80x256 pxl 40 µm pitch, Scan Buffer depth=4, Z=8) NO PANIC, JUST LOOK APSEL6D architecturesimulations Yellow = mind this Red = bad

11. C++ Hit controller reports run number 92 Matching hits 33066 Not matching hits 0 run number 93 Matching hits 33155 Not matching hits 0 run number 94 Matching hits 39827 Not matching hits 7892 run number 95 Matching hits 48387 Not matching hits 0 run number 96 Matching hits 48777 Not matching hits 0 run number 97 Matching hits 58168 Not matching hits 1781 run number 98 Matching hits 68629 Not matching hits 0 run number 99 Matching hits 79568 Not matching hits 17284 run number 100 Matching hits 80099 Not matching hits 44183 run number 101 Matching hits 57384 Not matching hits 66466 run number 102 Matching hits 401671 Not matching hits 0 run number 103 Matching hits 403273 Not matching hits 0 • Not matching hits only in those run with RO effi. < 100% (not matching = not found) GOOD, no corrupted hit by logic. • Cross check: Not-matching values over total hits confirm the efficiencies calculated by VHDL test bench APSEL6D architecturesimulations

12. 2D scan BCO vsRDclk @ 1MHz/mm2 APSEL6D architecture simulations

13. 2D scan BCO vsRDclk @ 1MHz/mm2 Frozen efficiency Safety Margin= % BCO period (us) BCO period (us) Determines the proximity to the BC_lost condition in the scan_buffer ( >100%  constant buffer overflow, < 100%  possible overflow due to burst) Reverse BC dependence APSEL6D architecturesimulations

14. Working status • DONE • Submatrix readout VHDL model for simulations and synthesis • VHDL and C++ test bench environment for deep investigation of the architecture behavior. • Simulations span for efficiency estimation (still running…) • TO DO • Output stage, compression and fast dequeuing. • Slow control code (register array, monitors, calibration integrated facilities, MP masking, pxl black list…) • Simulation of the whole chip functionalities APSEL6D architecture simulations

15. Summary • Overall good behavior of the architecture. (no misread hit, no SOS lost…) • Inefficiencies of readout: • Barrel 2 and1 overflow  100% efficient as far as twice the expected rate and at least 60 MHz RDclk. • Scan buffer overflow  depends on (mean_sweep_time(rate, RDclk *)/ BC period), must be safely < 1. Scan Buffer depth of 4 ensured NO BC lost for mean_sweep_times up to over 90% of BC period. (1 ms of simul.) • Freeze time ineff. can reach 99.5 % with 100MHz RDclk and 0,5 us BC. unfortunately, reverse BC dependence respect to scan buffer overflow probability. • Due to the expected rate and time-oriented sweep technique, 40MHz RDclk option is no more available for 1 us BC. (Scan buffer overflow) • 60 MHz RDclk, with 1us BCO ensures good performance (98.8% frozen efficiency (εlatch) @ 1MHz/mm2) and good margin on Scan Buffer overflow (mean sweep time/BC period ~ 0,75) * Depends also on MPx size and submat_x size APSEL6D architecturesimulations

16. BackUp Slides APSEL6D architecture simulations

17. MacroPixelsim waveform APSEL6D architecture simulations