EFFICIENT MODULO 2 n +1 SUBTRACTORS FOR WEIGHTED OPERANDS Costas P. Efstathiou

1. EFFICIENT MODULO 2n+1 SUBTRACTORS FOR WEIGHTED OPERANDS Costas P. Efstathiou Digital Systems and Communications Lab Department of Informatics Technological Educational Institute of Athens GREECE (HELLAS)

2. Application of the modulo arithmetic • Design of digital signal processors (DSP) based on residue number systems (RNS), where the moduli set {2n-1, 2n, 2n+1} is extensively used. • Correlation/convolution computation • Cryptographic algorithms The efficient design of the modulo 2n+1 components (adders, subtractors, multipliers, …) is challenging since they operate on wider (n+1)-bit operands.

3. Previously proposed modulo 2n+1 Subtractors • S. Timarchi, K. Navi, M. Hosseizade, "New Design of RNS subtractors for modulo 2n+1, in Proc. of 2nd IEEE Int. Conf. on Information and Communication Technologies, 2006. • E. Vassalos, D. Bakalis and H. T. Vergos, "Novel modulo 2n+1 Subtractors", Proc. of the 16th Int. Conf. on Digital Signal Processing (DSP), 2009

4. The most efficient of the previously proposed architectures1 1E. Vassalos, D. Bakalis and H. T Vergos, "Novel modulo 2n+1 Subtractors", Proc. of the 16th Int. Conf. on Digital Signal Processing (DSP), 2009.

5. Proposed modulo 2n+1 subtractor architecture

6. Design Methodology

7. Design Methodology (continued)

8. Resulting Inverted End Around Carry Save Adder

9. Simplifications for the inverted end around carry save adder The design of the SFA module is based on the observation that the elements of bit pairs (an, a0), (bn, b0) can not concurrently have the value 1

10. Final stage adder For the computation of the sum the vectors C, S are added by an inverted end around carry parallel adder. This adder computes the n least significant bits of the addition. The most significant bit is 1 when or when C+S=2n-1 or equivalently when vectors C, S are complementary. This condition can be easily detected, in the case of inclusive OR adders, as , while for the case of exclusive OR adders as Pn-1=1, where Gn-1,Pn-1 are the group generate, propagate signals at the most significant bit position of the inverted end around adder. In Inclusive OR adders the carry propagate signals are defined as pi=aibi, while in Exclusive OR adders as pi=aibi.

11. Architecture of the final stage adder

12. Resulting modulo 2n+1 subtractor architecture

13. Comparisons The comparisons are based on the commonly used unit-gate model. In the unit-gate model, the 2-input gates (NAND, AND, etc) count as one equivalent for both area and delay. The XOR, XNOR gates and the 2-to-1 multiplexer count as two equivalents. A full adder (FA) has area and delay complexity of 7 and 4 equivalents, while a half adder (HA) counts as 3 and 2 equivalents respectively. The SFA module counts as 7 and 4 gate equivalents. The design of the final stage adder is based on an exclusive-OR adder with a fast carry increment stage the carry computation unit of which is implemented according to the Ladner-Fisher parallel-prefix algorithm.

14. Area comparison in gate equivalents [1] E. Vassalos, D. Bakalis and H. T. Vergos, "Novel modulo 2n+1 Subtractors", Proc. of the 16th Int. Conf. on Digital Signal Processing (DSP), 2009

15. Delay comparison in gate equivalents [1] E. Vassalos, D. Bakalis and H. T. Vergos, "Novel modulo 2n+1 Subtractors", Proc. of the 16th Int. Conf. on Digital Signal Processing (DSP), 2009

16. AreaDelay comparison [1] E. Vassalos, D. Bakalis and H. T. Vergos, "Novel modulo 2n+1 Subtractors", Proc. of the 16th Int. Conf. on Digital Signal Processing (DSP), 2009

18. Thank you!