Design methods for modulo 2 n +1 multiply-add units C. Efstathiou, I. Voyiatzis, P. Prentakis

1. Design methods for modulo 2n+1 multiply-add unitsC. Efstathiou, I. Voyiatzis, P. Prentakis Department of Informatics, TEI of Athens, 12210 Egaleo, Athens,Greece Presenter : Prof. C. Efstathiou

2. Application of the modulo arithmetic • Correlation/convolution computation. • Cryptographic algorithms. • Design of digital signal processors (DSP) based on residue number systems (RNS), where the moduli set {2n-1, 2n, 2n+1} is extensively used. The efficient design of the modulo 2n+1 components (adders, multipliers, …) is challenging since they operate on wider, (n+1)-bit operands.

3. Demand for Efficient Multiply-Add Units • Efficient multiply-add units which perform the operation can facilitate common DSP and cryptography routines. Microprocessors which used in embedded systems contain a fast multiply-add unit. Long integer arithmetic would profit from a multiply-add-add unit which can carry out computation of the form . This kind of operation is performed in the inner loop of various algorithms of long integer arithmetic.

4. Proposed Architecture

5. Existing modulo 2n+1 multiplier architectures • For diminished-1 operands Array Architectures: Zimmerman (1999), Wang et al [1996], Efstathiou et al [2005], Sousa and Chaves [2005] Booth Architectures: Ma [1992], Sousa and Chaves [2005] • For conventional operands Array Architectures: Hiasat [1992], Wrzyszcz and Milford [1993], Efstathiou and Vergos [2007] Booth Architectures: Sousa and Chaves [2005] Our design is based on the array multiplier architectures for conventional operands.

6. Partial Products of XxY to be added modulo 2n+1 Terms from groups A, B, C, D cannot be 1 at the same time so they can be ORed instead of added.

7. Reduction of the partial product matrix (1)

8. Reduction of the partial product matrix (2) Introduced correction

9. Partial Products for Introduced correction -1

10. Carry save addition of the partial products The n partial products of XxY, operand Z=zn-1zn-2…z1z0 and the introduced correction vector are added modulo 2n+1 using a carry save adder (CSA) tree or array. According to the relation the output carries can be complemented and repositioned to the least significant bit position of the next addition introducing a correction -1. Therefore, the correction introduced by complementing and repositioning the n+2 carries of the carry save addition is –n.

11. Total correction computation Let C, S the output vectors of the multi-operand addition. The sum is computed by an inverted end around carry (EAC) adder. The correction introduced by the adder is -1. The introduced total constant correction is The term of the derived partial product array is included in the correction vector. The final correction vector is computed as

12. Partial products of the modulo 17 multiply-add unit

13. Architecture of the proposed modulo 17 multiply-add unit

14. Partial products of Introduced correction -3 Total correction =

15. Partial products of the modulo 17 multiply-add-add unit

16. Simplifications The FA which an input equal to 0 are simplified to HA modules, while those which has an input equal to 1 are simplified to HA+1 modules, which implement theand functions, and have the same complexity with the HA modules. The multiply-add-add unit design can further be simplified if the vectors zn-1zn-2…z1z0, wn-1wn-2…w0, and are used as inputs to the same carry save adder stage.