1 / 13

Energy Sum Algorithm

Energy Sum Algorithm. In all stages saturate outputs if input is saturated or arithmetic overflow occurs Operate on 40Mb/s data from LVDS de-serialisers : 88 channels per JEM, 9-bit E T data, parity, link error Latch incoming data on bunch clock, 2 samples per tick

clover
Download Presentation

Energy Sum Algorithm

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Energy Sum Algorithm • In all stages saturate outputs if input is saturated or arithmetic overflow occurs • Operate on 40Mb/s data from LVDS de-serialisers :88 channels per JEM, 9-bit ET data, parity, link error • Latch incoming data on bunch clock, 2 samples per tick • Select the stable sample under VME control • Automatic phase detection in f/w (remove that feature ?) • Delay scan (VME) • Correct for upstream latency differences, up to 3 ticks (shift register, VME controlled) • Send data to readout and spy circuitry • Zero data on parity error • Apply channel mask • Sum up electromagnetic and corresponding hadronic channel to 10-bit jet element • Multiplex jet elements to 80Mb/s and send to jet processor and backplane JEM FDR

  2. Energy Sum Algorithm (2) • Threshold jet elements and sum to ET (12 bits, 1GeV resolution) • Threshold jet elements and multiply (cosφ,sinφ), .25GeV resolution • Sum to 2*14 bit (EX,EY) missing energy vector • Transmit (EX,EY,ET) to sum processor • Calculate board-level total vector sum • Quad-linear encoding to 8 bit each • 6-bit value and 2-bit range indicator • Resolution 1,4,16,64 GeV, full scale 4 TeV • Send 25 bits of data incl. odd parity bit D(24) to backplane JEM FDR

  3. FPGA resources used • Fully synchronous designs, I/O Flip-flops used on all data lines • Input FPGAs XC2V1500-4FF896C • Slice Flip Flops: 27%  • LUTs: 59% total • IOBs 90% • Block RAMs: 68%  • Multipliers 50%  • GCLKs: 12%  • DCMs: 12% 40.6MHz • SUM FPGA XC2V2000-4BF957C • Slice Flip Flops: 7%  • LUTs: 11% total • IOBs 83% • Block RAMs: 12%  • GCLKs: 25%  • DCMs: 12% 42.8MHz JEM FDR

  4. Performance All interfaces and the algorithms have been tested on JEM1.0 in Mainz, at the RAL slice test and in the CERN test beam. Problems revealed: • SystemACE configuration fails if incoming clock or TCK signal are of insufficient quality : signal distortions confirmed re-layout of crystal clock and TCK distribution on JEM1.1 • At CERN 2 out of 4 PPR channels could not be received error-free : signal distortions confirmed modifications required on the PPR LCD module • Errors observed on ROI readout only recently : problems with on-JEM crystal clock distribution confirmed re-layout of readout module, use local clock Apart from the above problems all interfaces and the algorithms have shown to work error free in all tests JEM FDR

  5. Test setup Up to 3 JEMs in a 9U crate allowing for FIO tests either direction, along with VMM, TCM, CMM (and CPMs!) Control: Concurrent CPU on VMM or via flat cable External data sources for • TTC : TTCvx, TTCvi, TTCex (CERN/RAL) via TCM • LVDS : • 1 DSS 16-channel (MZ) • Several DSS (RAL) • LSM (RAL) • PPR (CERN) (4 channels) External data sinks for • Merger signals : 2 CMMs (RAL) • Readout path: • Complete ROS (RAL) • G-link tester with f/w pattern comparison (MZ) JEM FDR

  6. Test strategies • Test the full system including all interfaces and algorithms at moderate statistics. Generally use physics-like test vectors • Requires operation of a ROS and data comparison on a computer. Therefore even in relatively long test runs very low bit error rates would go undetected • Test interfaces with firmware-based test adapters and on-JEM diagnostic firmware allowing for real-time detection of pattern errors • These tests will reveal even low-level errors quickly Choice of test patterns - have a look at possible failure mechanisms: FIO data and merger data on backplane source-terminated lines at moderate speed: no signal dispersion expected nor observed 800 Mb/s readout data : due to optical transmission no dispersion expected nor observed LVDS links : the pre-compensation circuitry is required to compensate at a single time constant only, well below a single bit period. At the receiving end a slight overshoot should be observed • no inter-symbol interference expected on neither of the transmission lines. Main source of errors: system noise. Any non-constant data pattern should do. • Use binary counter pattern. Useful on serial links: • Has long stretches of many ones / many zeroes • Has transitions all-one to all-zero • Easy to detect errors JEM FDR

  7. System test at RAL (slice test) Setup with 2-stage merging in a single crate: DSS  JEM  crate CMM  system CMM  ROD  ROS  ROD  ROS Comparing readout data against simulation. ROD type : 6U modules Data format : old format (6U module specific) Results (June 2004): Data taken up to 5 slices of JEM DAQ data. Trigger rate up to 60kHz, 4*106 events analysed, no errors observed on JEM readout. JEM FDR

  8. Interface tests At RAL: Playback from JEM (ramps) into CMM (parity detection). Merger signals crossing 2/3 of backplane length: no error in 1013 bits In Mainz: FIO tests 3 JEMs (ramps, pattern comparison on central JEM) : no error in 1013 bits LVDS input tests Source : DSS, 16 inputs exercised at a time, pattern comparison (ramp) in input module : no error in 1015 bits Readout link tests : G-link tester with pattern comparison(ramp) no error in 1014 bits (problems with crystal clock from jet processor) JEM FDR

  9. FIO tests : delay scan All data latched into jet processor on a common clock edge Sweep TTCrx delay setting, 104ps steps Measure data errors on each channel : 10 bits, 5 signal lines Single channel 8ns error free All channels 6.5ns error free JEM FDR

  10. latency Latency Energy path 183ns Jet path 234ns < 9.5BC JEM FDR

  11. CERN test beam Within a wider test setup the following modules were available to generate / analyse JEM ‘test vectors’ based on true calorimeter signals PPR  JEM  CMM  CTP  ROD  ROS ROD type : 6U modules • Data received from PPR error free on 2 channels • Readout from PPR not possible  could not verify input signal integrity except parity error check • Energy sum signal processing verified internally JEM FDR

  12. Test beam results Sum algorithm error-free (see effects of quad-linear encoding) Energy sum to CMM Input data Eem+Ehad JEM FDR

  13. Production tests • Boundary scan at manufacturer: high coverage due to large fraction of scannable components  verify connectivity (static test) • Standalone tester for input module LVDS inputs, pattern comparison in firmware (high statistics) • Standalone tester for readout module, pattern comparison in firmware (high statistics) • DCI operation verified w. oscilloscope (drive unterminated 50 Ω cable into scope, record pulse shape) dynamic test • System-level tests in Mainz : 1 crate, 1 JEM supplied with LVDS data at a time, playback and spy facilities used to generate / capture data on board boundaries. • FIO delay scan • High statistics FIO BER tests, pattern detection in firmware, test full crate at a time with maximum activity on LVDS, VME, readout • System-level tests at CERN JEM FDR

More Related