PROGRESS ON ENERGY SUM ELECTRONIC BOARD

1. PROGRESS ON ENERGY SUM ELECTRONIC BOARD

2. Energy Sum In DAQ System 18 fADC VXS Backplane 16 CH 16 CH 16 CH 16 CH VME64 High Speed Serial Detector Signals VME64 Energy Sum 16 CH 16 CH 16 CH 16 CH Crate Sum to Trigger

3. Parallel Or Serial Transmission • Parallel Transmission • 16 ADC per fADC x 18 fADC = 288 wires • fADC data rate = 250 MHz => LVDS => 576 wires • Difficult if not impossible to design backplane • that balances 576 wires with each other and with clock • Serial Transmission • 36 LVDS wires • 16 bits * 250 MHz => 4 GBits/Second • VXS Bus Support up to 10 GBits/Second • Commercially available VXS backplane Xilinx FPGA V4 with 6.5 GBits/Second Transceiver is now available But VXS ?????

4. Exploring VXS PENTEK Scale Down Energy Sum fADC

5. Exploring VXS Step # 1. Exploring Pentek Step # 2. Design Scale DownEnergy Sum Step # 3. Test Scale Down Energy Sum Step # 4. Energy Sum Bit Error Test Step # 5 Energy Sum and Pentek Step # 6. fADC Loop Back Step # 7. 2 fADC and Energy Sum Step # 8. Design Full Energy Sum Step # 10. 18 fADC and Full Energy Sum

6. Step # 1. Exploring Pentek CONNECTOR WITH 8 WIRES CONNECTING TX PINS TO RX PINS (4 LANES) ChipScope Tx Rx JTAG DOUG CURRY PENTEK FPGA VHDL CODE • Test Result : • Tdelay = • Extra Data Tdelay XILINX Aurora MGT Transmit UserCLK Receive Status FIFO ADC 2.5 Gbits/Sec 3.125 GBits/Sec FIFO CLOCK XILINX CHIP SCOPE

7. Step # 2. Design Scale DownEnergy Sum XLINX MANUAL Energy Sum DOUG CURRY LINE SIM

8. Step # 3. Test Energy Sum HARDWARE SETUP Energy Sum CONNECTOR WITH 8 WIRES CONNECTING TX PINS TO RX PINS (4 LANES) DAC 2 SCOPE DAC 3 JTAG PC ENERGY SUM FIRMWARE SETUP FPGA VHDL CODE XILINX Aurora MGT Transmit UserCLK Receive Status MGT IS SET UP TO RUN AT 2.5 GBPS FOR TEST 1 3.125 GBPS FOR TEST 2 Data Generator Tx DAC2 Data Assembler DAC3 Rx XILINX CHIP SCOPE 156.25MHz CLOCK

9. Step # 3. Result Of Loop Back Test • DAC 1 and DAC2 Measurement with Tektronics SCOPE • Test 1 (2.5 GBPS) • DAC1 to DAC2 delay is 732 ns • DAC Clock (UserCLK) is 125 MHz • Test 2 (3.125 GBPS) • DAC1 to DAC2 delay is 580 ns • DAC Clock (UserCLK) is 156.25 MHz No Missing Data No Extra Data Measurement with CHIPSCOPE

10. Step # 3. Loop Back Test.DAC1 and DAC2 With TEK Scope

11. Step # 3. Loop Back Test.DAC1 and DAC2 With ChipScope

12. Step # 3. Loop Back Test.Resync Shown With ChipScope

13. Step # 4.Energy Sum Bit Error Test COLLECTOR CARD HARDWARE SETUP FPGA • XILINX • IBERT • Integrate Bit Error Ratio Tester • Tweaking MGT operating and electrical paramaters. DAC1 DAC2 Energy Sum CONNECTOR WITH 8 WIRES CONNECTING TX PINS TO RX PINS (4 LANES) DAC 2 156.25MHz CLOCK SCOPE DAC 3 JTAG PC MGT IS SET UP TO RUN AT 2.5 GBPS FOR TEST 3 3.125 GBPS FOR TEST 4

14. Step # 4 IBERT 2.5GBPS After 4 Hours

15. Step # 4 IBERT 3.125 GBPS After 4 Hours

16. Step # 5 Energy Sum and Pentek Pentek PC 1 PC 2 SCOPE GENERATOR 125MHz Energy Sum HARDWARE SETUP

17. Step # 5 Energy Sum and Pentek COLLECTOR CARD PENTEK CARD FIRMWARE SETUP FPGA VHDL CODE FPGA VHDL CODE XILINX Aurora MGT Transmit UserCLK Receive Status XILINX Aurora MGT Receive Rx Data UserCLK Transmit Tx Data Status Data Generator DAC2 4 Lanes 16bits / lane Data Assembler DAC3 GENERATOR 125MHz XILINX CHIP SCOPE XILINX CHIP SCOPE 156.25MHz CLOCK • 2.5 GBITS • Lane 0 => Constant 0xAAAA; Lane 1 => Ramp Up • Lane 2 => Constant 0xCCCC; Lane 4 => Ramp Down • DAC 2 and DAC 3 show RampUp sent and received

18. Step # 5 Energy Sum and Pentek. Result • USER_CLOCK is 125 MHz • DELAY FROM DAC 2 to DAC 3 is 134 USER_CLOCK (1.072 uS) • NO Missing Data • MGT never lost lock in 8 hours • MGT ReSYNC Interval is 4992 USER_CLOCK. Resync duration is 6 USER_CLOCK • CONCLUSION: • XILINX AURORA MGT CAN BE USED TO TRANSFER DATA FROM fADC TO ENERGY SUM.

19. To Be Continued Step # 6. fADC Loop Back Step # 7. 2 fADC and Energy Sum Step # 8. Design Full Energy Sum Step # 9. 18 fADC and Full Energy Sum