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NAND Flash Failure Behavior

NAND Flash Failure Behavior. Sponsored By Micron Technology Inc. Group Members and Topics. Rob Wells Project Introduction System Integration Jeremy Hamblin Firmware Design Roger White NAND DUT Interface NAND Controller & Timing David Chu Host GUI Interface & Application

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NAND Flash Failure Behavior

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  1. NAND Flash Failure Behavior Sponsored By Micron Technology Inc

  2. Group Members and Topics • Rob Wells • Project Introduction • System Integration • Jeremy Hamblin • Firmware Design • Roger White • NAND DUT Interface • NAND Controller & Timing • David Chu • Host GUI Interface & Application • Conclusions

  3. Robert Wells Project Introduction System Integration

  4. Introduction to NAND Flash • What NAND Flash Memory Is • NAND Flash Memory Applications • What NAND Flash Memory Is Not • Project Concept • An Affordable Platform • Customizable Usage/Programming Patterns • Characterization/Analysis of NAND Behavior

  5. System Integration • High Level View • FPGA System • Block Diagram Interface • SOPC Builder Overview • Component Generation • HAL (Hardware Abstraction Layer) – NIOS II • HDL (Hardware Description Language) – Quartus II • Quartus II Overview • Integration of the FPGA system • Controller Development • NIOS II Overview • Device Drivers • Firmware • Firmware to Controller Integration • Host PC to Firmware Integration

  6. High Level View • Components: • NIOS II Processor • SDRAM • USB • On-Chip Memory • LCD Display Quartus II .c • HAL (Hardware Abstraction Layer) • C Code • API (Application Programming Interface) • Firmware • Custom C Code • (Jeremy) .c .v SOPC .v NIOS II • HDL (Hardware Description Language) • Verilog Code • NAND Flash Controller • Custom Verilog Code • (Roger) • Application GUI Interface • Program the NAND Flash • Analyze/Display Results • (David) SOPC Builder (System On a Programmable Chip)

  7. High Level View • Configure Memory Usage • Memory Range • Data Pattern • Number of Cycles • Analyze Performance • Will NAND Flash Work Over the Lifespan of a Given Device? • Application GUI Interface • Program the NAND Flash • Analyze/Display Results • (David)

  8. System Integration • High Level View • FPGA System • Block Diagram Interface • SOPC Builder Overview • Component Generation • HAL (Hardware Abstraction Layer) – NIOS II • HDL (Hardware Description Language) – Quartus II • Quartus II Overview • Integration of the FPGA system • Controller Development • NIOS II Overview • Device Drivers • Firmware • Firmware to Controller Integration • Host PC to Firmware Integration

  9. FPGA development system Clock Generation SOPC Built System (Jeremy) Reset Delay NAND Flash Controller (Roger)

  10. System Integration • High Level View • FPGA System • Block Diagram Interface • SOPC Builder Overview • Component Generation • HAL (Hardware Abstraction Layer) – NIOS II • HDL (Hardware Description Language) – Quartus II • Quartus II Overview • Integration of the FPGA system • Controller Development • NIOS II Overview • Device Drivers • Firmware • Firmware to Controller Integration • Host PC to Firmware Integration

  11. Example FPGA System With SOPC

  12. System Integration • High Level View • FPGA System • Block Diagram Interface • SOPC Builder Overview • Component Generation • HAL (Hardware Abstraction Layer) – NIOS II • HDL (Hardware Description Language) – Quartus II • Quartus II Overview • Integration of the FPGA system • Controller Development • NIOS II Overview • Device Drivers • Firmware • Firmware to Controller Integration • Host PC to Firmware Integration

  13. System Integration • High Level View • FPGA System • Block Diagram Interface • SOPC Builder Overview • Component Generation • HAL (Hardware Abstraction Layer) – NIOS II • HDL (Hardware Description Language) – Quartus II • Quartus II Overview • Integration of the FPGA system • Controller Development • NIOS II Overview • Device Drivers • Firmware • Firmware to Controller Integration • Host PC to Firmware Integration

  14. System Integration • High Level View • FPGA System • Block Diagram Interface • SOPC Builder Overview • Component Generation • HAL (Hardware Abstraction Layer) – NIOS II • HDL (Hardware Description Language) – Quartus II • Quartus II Overview • Integration of the FPGA system • Controller Development • NIOS II Overview • Device Drivers • Firmware • Firmware to Controller Integration • Host PC to Firmware Integration

  15. Firmware to Controller Integration Controller Verilog Quartus II Firmware C Code NIOS II Buffer SOPC Builder

  16. System Integration • High Level View • FPGA System • Block Diagram Interface • SOPC Builder Overview • Component Generation • HAL (Hardware Abstraction Layer) – NIOS II • HDL (Hardware Description Language) – Quartus II • Quartus II Overview • Integration of the FPGA system • Controller Development • NIOS II Overview • Device Drivers • Firmware • Firmware to Controller Integration • Host PC to Firmware Integration

  17. Host PC to Firmware Integration Phillips ISP1362 (USB) WinDriver (Device Driver) SOPC Builder (HAL) NIOS II (Device Driver)

  18. Conclusions • System Components • Custom Hardware Design (Verilog) • Custom Firmware Design (C) • Powerful Design Tools • Custom Built Application GUI Interface • Inexpensive Platform for Testing • Analysis of NAND Wear-Out From a Customizable Memory Usage Model • Allows Developers to Determine if NAND Flash is a Viable Solution for a Given Application • Evaluate Other Aspects of NAND Flash

  19. Questions

  20. Jeremy Hamblin Firmware Design

  21. Firmware Design • SOPC Builder • System Components • Firmware Design (NIOS II) • Reset NAND Operation • USB Interface • Op-Code/Algorithm • NAND Flash Addressing • Example Algorithm Layout • Command Transferring

  22. SOPC Builder(System On a Programmable Chip) NIOS II Processor • Instruction & Data • Block Mapping & Status SDRAM Displays Global Reset USB Buffer Read Enable

  23. Firmware Design • SOPC Builder • System Components • Firmware Design (NIOS II) • Reset NAND Operation • USB Interface • Op-Code/Algorithm • NAND Flash Addressing • Example Algorithm Layout • Command Transferring

  24. Firmware Design • Reset NAND Operation • First Operation After NAND Power Up • Occurs During System Initialization • Places NAND DUT (Device Under Test) in a Known State

  25. Firmware Design • SOPC Builder • System Components • Firmware Design (NIOS II) • Reset NAND Operation • USB Interface • Op-Code/Algorithm • NAND Flash Addressing • Example Algorithm Layout • Command Transferring

  26. Firmware Design • USB Interface • Generates IRQ (Interrupt ReQuest) • ISR (Interrupt Service Routine) Receives Data Sent From Host PC and Parses Data 00 00 00 00 | 00 00 00 00 | 00 00 00 00 | 00 00 00 00 - 16 Bytes 00 00 00 00 | 00 00 0000 | 00 00 00 00 | 00 00 00 00 - 16 Bytes 00 00 00 00 | 00 00 00 00 | 00 00 0000 | 00 00 00 00 - 16 Bytes 00 000000 - Byte0 Padding Algorithm OP Code Start Address – 3 Bytes End Address – 3 Bytes Padding – 1 Byte # Cycles – 3 Bytes Padding – 5 Bytes

  27. Firmware Design • Op-Code Types • Read ID • Write • Read • Algorithm Types • Continuous • Checker Board • Random

  28. Firmware Design NAND Flash Addressing Blocks Pages Bytes

  29. Firmware Design • NAND Flash Addressing

  30. Algorithm Example Page N Page N-1 … Page 1 Page 0 Erased Programmed Block-0 Block-1 … Block N-1 Block N Continuous Cycle I Cycle II Checker Board

  31. Firmware Design • SOPC Builder • System Components • Firmware Design (NIOS II) • Reset NAND Operation • USB Interface • Op-Code/Algorithm • NAND Flash Addressing • Example Algorithm Layout • Command Transferring

  32. Firmware Design • Command Transferring • Commands & Data Transferred Through Buffer • Different Data and Command Requirements • Write- 2119 Bytes Transferred to NAND, 0 Returned • Read- 7 Bytes Transferred to NAND, 2112 Returned • Erase- 5 Bytes Transferred to NAND, 0 Returned • Read Status- 1 Byte Transferred, 1 Returned • Each NAND Command Type Has its Own Buffer Function • Removes All NAND Device Timing Constraints From the Firmware • Firmware Too Slow

  33. Firmware Design Conclusion • Command Received Over USB • Parsed in USB ISR • Execution of Op-Code • Command and Data are Passed to NAND Controller Through the Buffer • Command is Executed From Start Address to End Address • Repeated for # of Cycles Given in Command From Host • Block Status Returned Over USB

  34. Questions

  35. Roger White NAND DUT Interface NAND Controller & Timing

  36. NAND DUT Interface • Daughter Card • Our Own?? • Boise State’s

  37. NAND DUT Interface

  38. NAND Controller & Timing • Pins to NAND Chip • Operations

  39. NAND Controller & Timing • Pins to NAND chip • CLE (Command Line Enable) • CE# (Chip Enable) • WE# (Write Enable) • ALE (Address Line Enable) • R/B (Ready/Busy) • RE# (Read Enable) • WP# (Write Protect) • I/Ox (Input/Output)

  40. NAND Controller & Timing • Pins to NAND Chip • Operations

  41. NAND Controller & Timing • Operations • Read • Program • Erase • Read Status • Reset • Read ID

  42. NAND Controller & timing • Program Operation

  43. NAND Controller & Timing • Erase Operation

  44. NAND Controller & Timing • Reset Operation

  45. Conclusions NAND DUT Interface Daughter Card NAND Controller & Timing Pins Operations

  46. Questions?

  47. User Interface, USB, and Conclusions By: David Chu

  48. Overview • User Interface • Command Interface • Functionality and Scripting Information • Results Interface • Functionality, Database Information, and XML File Description • Charts Interface • Functionality • USB • Functionality and Bit Organization • Conclusions • Methods, Results, and Future Improvements

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