IEE5011 –Autumn 2013 Memory Systems Vertical (3D) NAND Flash Memories

1. IEE5011 –Autumn 2013Memory SystemsVertical (3D) NAND Flash Memories Yu-Jie, Liang Department of Electronics Engineering National Chiao Tung University s980650@gmail.com

2. Outline Introduction Overview of 3D NAND flash memory structure Gate stack type 3D NAND Flash (vertical) Channel stack type 3D NAND Flash (horizontal) 3D vertical floating gate NAND Flash Conclusion Reference

3. Introduction Fig.1 The trend of recent scaling.

4. Introduction • Planar NAND flash limitation: • Program disturb, read disturb, endurance degradation. • Interference due to the noise; cross-talk issue. • Dielectric reliability does not scale; breakdown problem and leakage paths. • Not enough of electrons. • Solution: • Die Stacking of 2D-NAND? • Use 3D IC technology? (TSV?) • Monolithic 3D IC technology • Integrally molded concept (TFT-SONOS) • BE-SONOS

5. Overview of 3D NAND flash structure • Gate stack type (vertical channel): • Bit cost scalable (BiCS) • Pipe-shaped Bit cost scalable (P-BiCS) • Vertical stack array transistor (VSAT) • Terabit cell array transistor (TCAT) • Channel stack type (horizontal channel): • Vertical Gate (VG) • Single Crystalline Stacked Array (STAR)

6. Overview of 3D NAND flash structure • Gate stack type VSAT P-BiCS TCAT • Channel stack type VG

7. Bit cost scalable (BiCS) Fig.2 Bit Cost scalability of three dimensional flash memory.

8. Bit cost scalable (BiCS) Fig.3. Architecture of BiCS and Schematic of NAND memory • BiCS limitation: • Small P/E window, read disturb, low data retention capability. • Variations in the voltage on the source line. • Lower select gate in heavily doped is not easily controlled.

9. Pipe-shaped Bit cost scalable (P-BiCS) Fig.4. Schematics of (a) BiCS (b) P-BiCS • Large P/E window, high speed, high data retention. • Read disturb of P-BiCS is sufficient for MLC operation.

10. Terabit Cell Array Transistor (TCAT) • The metal gate structure • For good erase speed, wider Vth margin, and better retention • But difficult to etch metal/oxide multilayer simultaneously. • GIDL erase method • Extra area to apply negative bias on WL. Fig.5. Architecture of TCAT

11. Limitation of Gate stack type BiCS suffers from WL interconnect, program disturbance, and channel resistance problem. The channel current of P-BiCS and TCAT is conducted through a hole drilled through the layers and an additional WL-cut process must be applied to isolate the WL’s in the X direction. They have limited in X pitch scalability due to the corresponding lithography overlay issue involved. The cell size of all vertical channel architectures is 6F2. It is not suitable for the traditional planar NAND cell size. (minimum F= 40nm~50nm) Low read current: As increase in the length of the NAND string, the read current degrades.

12. 3D VG NAND Architectures Fig. 8 Dumb mode (without any P/E verify) P/E distributions of 3D VG NAND devices.. Fig.6. Architectures of VG charge trapping NAND flash. • Problems: • Wider distribution caused by grain boundary effect. • To isolate the SSL gate in X direction. The X pitch scalability will be limited (A) Using junction-free buried channel device [7]: Fig. 7 Read current with various channel doping.

13. 3D VG NAND Architectures • (B) Using PN diode decoding structure [8]: Fig.10. Poly silicon PN diode I/V characteristics Fig.9. Architectures of the PN diode decoded VG NAND architecture. • A good PN diode with very low leakage is very important.

14. 3D VG NAND Architectures • (C) In-layer plural normally-on SSL decoder[6]: • The first proposed VG NAND uses plural SSL gates • BL in multi-layers can be shared together. Fig.11. Schematic diagram of in-layer normally-on SSL decoder for VG NAND • Problems: • SSL devices must be kept in a complex normally-on status. This introduces a linearly increased layer cost. • As the number of stacked layer increases, the number of SSL gate is increased accordingly. • Normally-on SSL uses heavy N+ implant in the channel, thus requires careful thermal budget control.

15. 3D VG NAND Architectures • (D) Island-gate SSL decoding method [9]: • Each channel BL has its own island-gate SSL for the selection/decoding. • As the number of stacked layer increases , the memory layer does not increase the array overhead size but simply change the unit and page number. Fig.12. Schematic diagram of 3DVG NAND using island-gate SSL decoding method • Problems: • The island-gate SSL decoding suffers BL pitch scaling limitation due to the overlay concern between SSL devices.

16. 3D VG NAND Architectures • (E) Self-aligned IDG SSL decoding method [10]: • The top portion of the SSL poly gate is removed by an additional mask after WL patterning. Fig.13. Schematic structure of the IDG decoded VG NAND Flash. • Need careful optimization of turn-on voltage (+VSSL) and inhibit bias (-Vinhibit) in order to cover the often broad IDG (TFT) SSL Vt distribution.

17. Summary of 3D VG NAND decoding Architectures • In (B), (D), (E), the area is largely fixed when stacking more layers. These fundamentally solve the issues in (C) and become more cost effective when stacking more layers. • In (B), (C), page operation is carried out in one memory layer each time. In (D), (E), page operation is carried out within all memory selected by one island-gate SSL in one unit, while many parallel units are programmed/read simultaneously.

18. STAR NAND flash Architecture Fig.14. (a) Unit structure of 3D NAND Flash memory based on STAR, i.e., “building.” (b) Equivalent circuit of the building and operation voltage scheme table.

19. Advantages of STAR over VG NAND • (1) Single-crystal channel: better performance without grain boundaries. • (2) Gate-all-around structure (GAA): good current drivability and small sub-threshold swing. • (3) Small intra-layer interference: • (4) No inter-layer interference: • (5) Small channel to channel coupling:

20. 3D FG type NAND • (A) Extended Sidewall Control Gate (ESCG): Fig.15. (a) Bird’s-eye view and (b) cross-sectional view of 3D vertical FG-type cell using ESCG. Fig.16. Cross-sectional views of the coupling capacitance of the FG. • Better CG coupling ratio. • High-speed read/program operation, less interference effect and good reliability.

21. 3D FG type NAND • (B) Separated Sidewall Control Gate (SSCG): Fig. 17. Three-dimensional vertical FG NAND with SSCG. (a) Bird’s eye view and (b) cross-sectional view in WL direction and (c) equivalent circuit of cell arrays.

22. Conclusion

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25. Thank you