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SRAM Design for SPEED

SRAM Design for SPEED. GROUP 2 Billy Chantree Daniel Sosa Justin Ferrante. The Bitcell. The Bitcell (cont.). 6-Transistor Design M 1 and M 5 are 3 micron wide, 600 nm long M 2 and M 6 are 1.5 micron wide, 600 nm long M 3 and M 4 are 1.5 micron wide, 750 nm long

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SRAM Design for SPEED

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  1. SRAM Design for SPEED GROUP 2 Billy Chantree Daniel Sosa Justin Ferrante

  2. The Bitcell

  3. The Bitcell (cont.) • 6-Transistor Design • M1and M5 are 3 micron wide, 600 nm long • M2 and M6 are 1.5 micron wide, 600 nm long • M3 and M4 are 1.5 micron wide, 750 nm long • Cell Ratio = (W1/L1) / (W5/L5) • Pull Up Ratio = (W4/L4) / (W6/L6) • Yields CR = 2.5, PR = 1.2 • Well within constraints of CR > 1.2, PR < 1.8 • Needed to ensure read stability while retaining ability to write to the cell • By not choosing values such that CR and PR are at their limits, the bitcell becomes more robust with respect to variation.

  4. The Voltage Sense Amp

  5. The Sense Amp (cont.) • Design Specs • 9-Transistor S/A • Cross-coupled Inverters • One per Block Column (i.e., mult. reads) • ~2ns Total Propagation Time • Why? • Simplicity (over multi-stage S/As) • Size (area, power savings)

  6. Tri-State Write Driver

  7. Tri-State Write Driver (cont.) • Design Specs • 36-Transistor WD (w/buffering) • Write Control / Driver Sections • ~2ns Total Propagation Time • Why? • Simplicity • Efficiency

  8. The Decoders

  9. Row Decoder • Composed of 2 to 4 NOR Predecoders and 3input NAND gates • Fanout Reducing Buffers • Enable Embedded Buffers

  10. Column Decoder • NMOS Pass Transistor Based

  11. The Control Logic WRITE DRIVER CONTROL PRECH GENERATOR

  12. The Control Logic (cont.) • Design Specs • Used to control signals (e.g., WD_C) • Used to generate signals (e.g., prech) • Why? • Necessary for signal synchronization • Do NOT impede READ/WRITE cycle time (i.e., control signals are processed alongside existing delays)

  13. Sense Amp Enable Logic - Consists of an AND gate, buffers, and the Prech and Read signals. - In a read operation, the precharge signal will go low in order to precharge the bitlines, then returns high. - The read signal goes high before precharge in order to accelerate overall clock speed. Before it reaches the AND gate in this logic, it is buffered several times to delay the firing of the sense amplifier. - This allows a differential voltage between the bitlines to form before the sense amp fires, thereby providing correct operation.

  14. With Your Powers Combined…

  15. Metric Table

  16. Ideas for Improvement • Registers to latch output of SRAM • Shortening read cycles and clock period • Depends on setup time and hold time of the registers, reducing precharge lengths • Replace voltage sense amps with current sense amps

  17. Any Questions?

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