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JEM PRR

JEM PRR. Design changes Post-FDR tests FDR issues. Post FDR JEM design changes. JEM modifications 1.1  1.2: Increase PCB layer count : 14 layers (FIO cross talk) Increase FIO track spacing : minimum .45mm (FIO cross talk)

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JEM PRR

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  1. JEM PRR • Design changes • Post-FDR tests • FDR issues

  2. Post FDR JEM design changes JEM modifications 1.11.2: • Increase PCB layer count : 14 layers (FIO cross talk) • Increase FIO track spacing : minimum .45mm (FIO cross talk) • Improve input daughter connector grounding by adding vias (FIO noise) • Increase merger track spacing : .45mm (cross talk on merger lines) • Upgrade jet processor to XC2V3000 to use external voltage reference on FIOs (FIO noise) • Connect Vbatt of processors to ground (change of device specifications) JEM modifications 1.21.3: • New TTCdec mounting holes (specification change) • Add missing FIO track (design error) • Supply VME bus buffers from separate 3.3V regulator to allow for control of the switching regulators via CAN (pre-caution to deal with non-reproducible issue of FPGAs not configuring up, seen exactly once) • Increase CAN TX/RX track spacing (design error)

  3. Post FDR daughter module design changes Input Module modifications 1.01.1: • Improve ground blade connection (FIO noise) • Add SMB voltage sensor • Connect Vbatt to ground (change of device specifications) Readout Module modifications • 1.01.1: • Go for 4-layer PCB (FDR) • Add link ready / laser-on LED • 1.11.2: • Use impedance controlled tracking Control module • initial design • 6 layers auto routed • CPLD, CAN controller, buffers

  4. Tests : signal integrity : merger lines Due to cross talk and noise on JEM1.1, the current version JEM1.2 was thoroughly tested for signal integrity issues. • Merger lines: cross talk down to 50% of previous figure: ~300mV into 2.5V signal (source terminated victim line, all others switching) JEM1.1 JEM1.2 100mV/div 200mV/div

  5. Tests : signal integrity : FIO lines • FIO lines use 1.5V signalling • Noise 320mV into signal (series terminated victim line, all others switching) • Use HSTL sensing on jet FPGA : +/-100mV sensitivity 100mV/div 12.5ns/div

  6. Latency measurement Latency measured from LVDS input pins to backplane connector: TDR figures almost met: • 256.6 ns rather than 250 ns for jet processing • 182.2 ns rather than 200 ns for sum processing Jet : 256.6ns Sum : 182.2ns

  7. System tests 4 post-FDR test sessions at RAL. Aim: • Test a JEM with all of its LVDS inputs populated from an LSM, and measure bit-error rates in the presence of backplane FIO traffic. • Repeat the backplane fan-in/fan-out test with heavy backplane traffic and LVDS inputs present. • Extend other tests to use more data patterns, making them as ‘stressful’ as possible. Setup: • 2 CMMs • 2 JEMs1.0 • 1 JEM1.2 (central position) • 1 LSM supplying JEM1.2, all 88 channels • Readout into 9U ROD • DAQ outputs of 2 CMMs and 2 JEMs (1 JEM1.0 DAQ-out broken) • ROI outputs from all 3 JEMs

  8. System tests : setup Try and cover all required tests in a single system test rather than individual interface tests. Test setup optimised for maximum of noise and sensitivity: • Generate VME traffic (read CMM continuously) : this activity was running for fraction of the tests only • Fill 2 JEM’s playback memories with special pattern • Fill 1 LSM with special pattern • (Almost) all channels switching 1/0/1/0 on all FIO lines concurrently • One jet per JEM • Jet thresholds tuned such that we are sensitive to bit errors • Read out the full setup and compare to simulation • Read error counters on input modules to check for parity errors in events that couldn’t be analysed in software • Read CMM error counters

  9. System tests : results Result: It took a while to persuade the 9U ROD / the online software to do runs over several hours Eventually we were successful: 1 overnight run of 141 million events with no data transmission errors on any of the interfaces. Error counters didn’t show any parity errors EXCEPT A single LVDS input channel generating errors. Seen on parity error counters and in software comparison This was the last night of the November test session. No chance to do further measurements. However Channel confirmed to be broken back home. Was on a module that had been swapped just before that run. Seems we replaced a working input daughter by a defective one.

  10. System tests What’s missing ? • Never tested traffic between two ‘low noise’ modules (1.2) • ‘low noise’ input module 1.1 is not yet existent • JEM 1.3 carries a few bug fixes • That’s minor modifications only. Should have improved noise figures • Tests would require a few JEMs to be built (minimum of two) • Pre-production of four required anyway • Build pre-production modules NOW • Repeat all tests within the scope of the required ‘full crate test’ • Have a test with a jet merger • Have well-prepared semi-automated tests since there is little time to waste

  11. Other FDR issues • Make readout and control module multilayer • Improve extraction handles • Slot keying • Leave unused LVDS inputs open • Turn off parallel buses on TTCrx • Improve speed margin on processor FPGAs • Sort out backplane grounding • Sort out Pre-processor LVDS specifications • Work on latency • Power inrush / power sequencing • Power consumption during configuration • Provide documentation / update specifications

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