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Hybrid CMOS-SET Devices and Circuits: Modelling, Simulation and Design

Hybrid CMOS-SET Devices and Circuits: Modelling, Simulation and Design. Santanu Mahapatra. Outline. Introduction: CMOS scaling and emerging devices Single Electron Transistor (SET) Compact Modelling of SET CMOS - SET Hybrid Architectures CMOS - SET co-Simulation

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Hybrid CMOS-SET Devices and Circuits: Modelling, Simulation and Design

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  1. Hybrid CMOS-SET Devices and Circuits: Modelling, Simulation and Design Santanu Mahapatra

  2. Outline • Introduction: CMOS scaling and emerging devices • Single Electron Transistor (SET) • Compact Modelling of SET • CMOS - SET Hybrid Architectures • CMOS - SET co-Simulation • SETMOS – A Novel Hybrid CMOS-SET Device • Implementation of MV logic and Memory by SETMOS • SET Technology – CMOS-SET co-Fabrication • Conclusion

  3. Key problems of for sub-10nm MOSFET (i) electrostatic limits (ii) source-to-drain tunnelling (iii) carrier mobility (iv) process variations (v) static leakage (vi) Power density Introduction Pushing CMOS: the 10 nm wall After J.D Plummer , Proc IEEE 2001 Aggressive scaling has pushed CMOS device dimensions towards sub-10nm limits

  4. Life with and after CMOS

  5. Island Gate Gate dielectric Drain Source Ultra thin dielectric Single (Few) Electron Transistor

  6. many electrons simultaneously • participate to conduction • gate potential invert the channel • junctions highly transparent • mainly gate controls the threshold • electron conduction is one by one • island is conductor, VG only changes the potential and thus controls tunneling • needs opaque junctions: RT > RQ~26kW • drain/gate controls Coulomb blockade SET vs. MOSFET: Device Perspective

  7. Engineers Like Numbers…. • RT > RQ = h/e2 = 26k • e2/C > kBT  C < e2/ kBT • where  = 10 (Memory Application), 40 (Logic Application) Present Tech. RT = 0.5-1M C = 2-3 aF

  8. IDS vs. VGS @ #VDS IDS vs. VGS @ #T Characteristics of SET (1) IDS vs. VDS @ #VGS CTD= CTS= 1aF, CG= 2aF, RTD = RTS = 1M

  9. Characteristics of SET (2) Background Charge (BC) effect When BC is integer (n) there are no change in SET characteristics, however, it experienced a shift of (BCeffe)/CG on VGS axis when BC is fractional. For proper operation, BC < n + 0.1e A second gate with proper bias can compensate the B.C. Effect!

  10. constant D I S D I S D I S 3 3 3 2 2 2 2 1 1 4 6    1 2 3 3 5 0 0 0 2 4 - - - Carrier Transport in SET VIS = (CG/C)VGS + (CTD/C)VDS  = e/(2C); VD =  ; VS = 0 Tunneling occurs only when lVISl or lVDIl>  ON OFF (C.B.) ON

  11. SET Simulation Techniques A successful implementation of SET as a post-CMOS VLSI Candidate demands spice-compatible COMPACT analytical models

  12. ID IS IDIS IDS = ID + IS IDS ID = VD/RD IS = VS/RS  2 At T <<e2/C , VD and VS are either positive or zero SET Compact Analytical Model- MIB* • Based on the Orthodox theory, i.e., charge discrete, energy continuous, etc. D I S VS  IS ID 0 VD - *S. Mahapatra et al. EDL 02, IEDM 02,TED 04

  13. The Complete MIB Model and where VT is thermal voltage and  holds the sign of VDS Model is valid for VDS 3e/C and T < e2/(10kBC)

  14. Model Verification IDS vs. VGS @ #VDS IDS vs. VGS @ #T Symbol: MC Solid Line: Analog MIB Dotted Line: Digital MIB CTD= CTS= 1aF, CG= 2aF, RTD = RTS = 1M

  15. VSS = e/2(CG + CT) Vout Vin VSS = e/2(CG + CT) CTS = CTD = CT SET INVERTER

  16. Power Dissipation in SET Logic* (1) There is a non-zero static current from VDD to VSS when the SET inverter is in Logic HIGH or LOW, however this static current is zero during logic transition, which is just opposite to the CMOS inverter. *S. Mahapatra et al. IEDM 02, DAC 02

  17. Power Dissipation in SET Logic (2)

  18. Power Dissipation in SET Logic (3) • Static Power Dissipation (Pstatic) • Dynamic Power Dissipation (Pdynamic) • Temperature Induced Leakage Power Dissipation (Pleakage) • Ptotal = Pstatic + Pdynamic + Pleakage In SET logic, power dissipation is essentially static: (~ 10-8 W), which is almost 4-5 decades lower than CMOS!

  19. Room temp. operation (randomness increases with temp.) • RTS ratio greater than one decade (highest) SET Random Number Generator* *Toshiba, IEDM 02

  20. CMOS & SET: Competitor/Collaborator?

  21. Concept of Hybrid CMOS-SET Architecture • Practical SET digital circuit applications are likely not feasible with a pure Single Electronics approach, mainly due to its low current drive • Combining SET and CMOS, and exploiting the Coulomb Blockade oscillation phenomenon of SET and high current drive facility of CMOS, one can bring out new analog functionalities, (neuron cell, Multiple Valued Logic) which are very difficult to implement by pure CMOS approach.

  22. Challenges of Hybrid CMOS-SET Architecture Design • Enable advanced SET/CMOS co-simulation and design • Development of common technological platform • Innovation on new functionalities of hybrid IC architectures, which are really un-paralleled to the pure CMOS circuits.

  23. CMOS-SET Co-simulation* (1) • Proposed model MIB is implemented in SMARTSPICE** through its Verilog-A (AHDL) interface • It is assumed that interconnect capacitances at gate, source and drain terminals are much bigger than the SET device capacitances. Therefore SET characteristics depends only on the nodal voltages. • Model parameters are device capacitances (CG,CG2, CTD,CTS), device Resistances (RD,RS) and Background Charge which could be defined through the SPICE MODEL CARD. * S. Mahapatra et al., ICCAD 03 **SILVACO International

  24. CMOS-SET Co-simulation (2) SMARTSPICE simulation flow

  25. Circuit Simulation: Neuron Cell * M. Goossens, Delft University Press SET : CG = CG2 = 0.04aF, CTD = CTS = 0.02aF, RD = RS = 1M PMOS: L = 0.5m, W = 0.8m, TOX = 9.74nm, VTH = 0.55

  26. Memory Quantizer Circuit Simulation: MVL Cell SET: CG = 0.27aF, CTD = CTS = 2.7aF, RD = RS = 200k NMOS: W = 12m, L = 14m, Tox = 90nm, VTH = 0.64V VGG is set to 1.08V and Vout is hard-limited at 5V *H. Inokawa et al., TED ‘03

  27. EPFL’S Variable Hysteresis Cell* CG = 0.2aF, CTD = CTS = 0.15aF, RD = RS = 1M S. Mahapatra and A.M.Ionescu et al. JJAP’04, IEEE NANO ‘04

  28. If VDS1,MAX <= VTH, MOS is operating just under VTH (subthreshold) SETMOS Device – C.B. at A Range! S. Mahapatra et al., IEDM 03, EDL 04

  29. SETMOS Device Characteristics (1) IDS vs VGS @ #VDS CG = 0.2aF CTD = 0.15aF CTS = 0.15aF RD = 1M RD = 1M L = 65nm W= 100nm VTH = 0.32V TOX = 1.7nm Calibrated 65nm BSIM4 model [BSIM Web] C = 0.5aF Ø ~ 2.5nm

  30. SETMOS Device Characteristics (2) IDS vs. VGS @ #T CG = 0.2aF CTD = 0.15aF CTS = 0.15aF RD = 1M RD = 1M L = 65nm W= 100nm VTH = 0.32V TOX = 1.7nm • Sub Ambient (00C to –1500C) Operation: • Realistic SET (Ø ~ 2.5nm) • Improved MOS Characteristics in terms of SS, PDP, leakage [I.Aller et al., ISSCC ‘00 ] 1000C

  31. At sub-ambient temp. • Mobility increases • Static Power dissipation decreases • Sub. Slope improves • Speed increases New Architectures BULK Roadmap Sub-ambient operation Sub-ambient operation of CMOS Y. Taur and E.J. Nowak, IEDM 97

  32. SETMOS NDR Device

  33. Gate Leakage Effect SETMOS NDR Device Characteristics IIN vs. VIN @ #IBIAS No impact of leakage IG < IBIAS/10

  34. After K. Banerjee et al. Proc. IEEE 2001 Interconnect Issues in Nanoscale ICs Not only the fundamental limitations of the nano-scaled MOSFET, but also the interconnect limits have threaten to decelerate or halt the historical progression of the semiconductor industry because the miniaturization of interconnects, unlike transistors, does not enhance their performance As larger the chips become, the number of local modules grows as l2 (where l is the chip edge length) and the number of interconnects in a generally connected network grows as (l2!)

  35. Multiple Valued (MV) Logic: Motivation MV Logic is a logic system where the radix is more than 2. radix (r) = 2 (binary), 3(ternary), 4 (quaternary) Analog Binary MV The information per line carried by binary system (either 0 or 1) is much less than analog system (infinity). That’s why interconnect complexities have always been a problem in Digital (Binary) ICs than Analog one. However, digital systems have other advantages compared to the analog counterpart in terms of precision, stability, noise immunity etc. BUT ARE THOSE ADVANTAGES SOUGHT TO BE FOUND ONLY IN THE BINARY DOMAIN????

  36. MV Logic Applications • Complete replacement of Binary world by MV logic may not be possible, however a hybrid binary-MV system can be used to solve the interconnect complexities. • Large scale memories, Content Addressable Memories • Neural Network, Intelligent Systems • Advanced systems, e.g., molecular computing system Pass Gate 0 (if s=si and e = ei) s (otherwise) s0, s1,……..sk (substrates) e0, e1,……..ek (enzymes)

  37. MV Logic Implementations • Concept of MV logic is NOT AT ALL very new, however its CMOS implementation has always been strugling because: • MOSFET is a single threshold device • CMOS implementation of MV logic either demands MOSFETs having different threshold voltage on the same wafer or highly asymmetric (like 200:1) device aspect ratio. However, the Coulomb blockade oscillations (multiple threshold points) could be directly linked to MV operations. SETMOS, which combines the features from both SET and CMOS could be an attractive candidate for MV logic and memory realization.

  38. Working Principle: SETMOS Quaternary Literal Gate* (1) Literal Gate (axb) : f(x) = r –1 when when axb else 0 Universal Literal Gate (xs): f(x) = xs = r 1 when x = s  S else 0 Here, for quaternary logic system, r = 4, S = (0,1,2,3), and a, b, x, sS. Example: if x = (0,1,2,3) 2x3=(0,0,3,3) and x1,3= (0,3,0,3) *S.Mahapatra and A.M.Ionescu, submitted to TNANO

  39. SETMOS Quaternary Literal Gate (2) 04 = 0V, 14 = 0.3V, 24 = 0.6V, 34 = 0.9V Using literal gates one can implement the Transmission Gate (T-Gate) which is a building block of all MV logic functions.

  40. Binary-to-Quaternary Converter 04 = 0V, 14 = 0.3V, 24 = 0.6V, 34 = 0.9V 04 = 0V, 14 = 0.9V

  41. Quaternary-to-Binary Converter

  42. Interconnect Reduction Scheme Traditional Binary System Local Interconnects Global Interconnects Hybrid Binary-MV System

  43. SETMOS MV SRAM (1) NDR Hysteresis

  44. SETMOS MV SRAM (2)

  45. SETMOS MV SRAM (3) • IR~1A (100 times larger than some other MOS-SET approaches) • Writing is ideally instanteneous, Reading time is in the same order of conventional CMOS SRAM • Minimum Transistors needed to develop one SRAM cell by pure CMOS approach is 12 [U. Cilingiroglu, IEEE CAS II, 2001]

  46. E P F L SET Technology • Unlike CMOS, there is no fixed, well defined technology for SET fabrication • SET could be made by Si, Metal, III-V Material or even by Carbon Nanotubes Some of the possible Si-SET technologies are: • PADOX – SD [NTT] • Undulated Film – MD [Toshiba] • Nano-grain PolySi – MD [Hitachi] • Electronic SET – SD [Korea] • MOS-SET – SD [LETI] SD : Single Dot MD: Multiple Dot

  47. Single Dot SET Fabrication (1) FEEL THE CHALANGE !! ISOLATE 8 inch 5nm 0.4mm SET island Si/SOI wafer LITHOGHRAPHY IN THREE DIMENTIONS ??

  48. Single Dot SET Fabrication (2) PAttern Dipendent OXidation (PADOX)* Idea  stressed silicon has a lower oxidation rate *NTT Japan EPFL’s Approach : (i) no e-beam (ii) smaller island size

  49. Multi Dot SET Fabrication (1) Multi Dot Device: Non-classical SET Advantage: Easier to fabricate than single dot device Difficulties: Modelling and Design

  50.  = 10-20nm Multi Dot SET Fabrication (2) EPFL’s nano-grain polysilicon wire technique

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