1 / 17

IKI20210 Pengantar Organisasi Komputer Kuliah Minggu ke-5a: Prosesor

IKI20210 Pengantar Organisasi Komputer Kuliah Minggu ke-5a: Prosesor. Sumber : 1. Hamacher. Computer Organization , ed-4. 2. Materi kuliah CS152, th. 1997, UCB. 2 Oktober 2002 Bobby Nazief (nazief@cs.ui.ac.id) Johny Moningka (moningka@cs.ui.ac.id)

cosmo
Download Presentation

IKI20210 Pengantar Organisasi Komputer Kuliah Minggu ke-5a: Prosesor

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. IKI20210Pengantar Organisasi KomputerKuliah Minggu ke-5a: Prosesor Sumber:1. Hamacher. Computer Organization, ed-4.2. Materi kuliah CS152, th. 1997, UCB. 2 Oktober 2002 Bobby Nazief (nazief@cs.ui.ac.id)Johny Moningka (moningka@cs.ui.ac.id) bahan kuliah: http://www.cs.ui.ac.id/~iki20210/

  2. Outline Materi Kuliah (revisi) Tugas Pemrograman #1: Data X’fer, A&L #2: Condition & Branch #3: SubRutin #4: I/O #5: Proyek Kelompok 04-09-02 11-09-02 18-09-02 25-09-02 02-10-02 09-10-02 16-10-02 23-10-02 13-11-02 20-11-02 27-11-02 18-12-02 01-01-03 08-01-03 15-01-03 01. Pendahuluan (1) 02. Set Instruksi (2.1 – 2.4) 03. Bahasa Rakitan AVR 04. Assembler (AVR Assembler) 05. Prosesor (3) 06. Prosesor (3) 07. Memori (5) 08. Memori (5) 09. I/O (4) 10. Aritmatika (6) 11. Aritmatika (6) 12. Interupsi, Peripheral (9) 13. Pipeline (7) 14. Dukungan HLL/OS 15. Reserve

  3. Solusi PR #1 CO: [75] (2.2) 0010 1100 = 0x2C = 44, ‘,’ (koma) (2.3) [1000]=‘J’, [1001]=‘o’, [1002]=‘h’, [1003]=‘n’, [1004]=‘s’, [1005]=‘o’, [1006]=‘n’ (2.5) Load A ; Acc  [A] Multiply B ; Acc  [A] x [B] Store TMP ; TMP  Acc Load C ; Acc  [C] Multiply D ; Acc  [C] x [D] Add TMP ; Acc  Acc + [TMP] (2.10) ; R1=1200, R2=4600 Move 20(R1),R5 ; EA=1200+20=1220 Load #3000,R5 ; 3000 ada di dalam instruksi Store R5,20(R1,R2) ; EA=1200+4600+20=5820 Add -(R2),R5 ; EA=4600-1=4599 Sub (R1)+,R5 ; EA=1200

  4. Solusi PR #1 CO: (2.14)a. Load R1,(R5)+ ; pop item #1 Load R2,(R5)+ ; pop item #2 Add R1,R2 ; R1  R1 + R2 Store -(R5),R1 ; push R1 (2.14)b. Load R3,4(R5) ; R3  M[R5+4] ; R5+4 points to item #5 (2.14)c. Add R5,#10 ; R5  R5 + 10 ; R5 points to item #11 ; item #1 is at TOS

  5. Solusi PR #1 Instruksi AVR: [25] • Arithmetic & Logic (10) ADD, ADC, SUB, SBC, SUBI, AND, OR, INC, DEC, CLR • Data Transfer (10) MOV, LDI, LDD, STD, LD, ST, LDS, STS, LD X+, ST X+, LD –X, ST –X • Branch (10) BREQ, BRNE, BRGE, BRLT, RCALL, ICALL, RET, RJMP, IJMP, BRSH • Bit & Bit-test (10) CLC, CLZ, CLN, BCLR, SEC, LSL, LSR, ROL, ROR, ASR

  6. Tugas Lab. No. 1 • Inisialisasi data: Register: r1=r2=0, r26=r27=r28=r29=r30=r31=0xFF Memori: [0x0060]=0x01, 0x10, 0x03[0x0063]=0x0F, 0x70, 0xFD[0x0066]=0xFF, 0xFF, 0xFF • Inspeksi isi register: r1, r2, Flags (H,S,V,N,Z,C), X, Y, Z, PC • Inspeksi isi memori: M[0x0066], M[0x0067], M[0x0068] • .DSEG • x: .BYTE 3 • y: .BYTE 3 • z: .BYTE 3 • ; • .CSEG • ldi XH,high(x) • ldi XL,low(x) • ldi YH,high(y) • ldi YL,low(y) • ldi ZH,high(z) • ldi ZL,low(z) • ld r1,X+ • ld r2,Y+ • add r1,r2 • st Z+,r1 • ld r1,X+ • ld r2,Y+ • add r1,r2 • st Z+,r1 • ld r1,X+ • ld r2,Y+ • add r1,r2 • st Z+,r1 • nop

  7. Prosesor

  8. Computer Processor (active) Memory (passive) (where programs, data live when running) Devices Input Control (“brain”) Datapath (“brawn”) Output Prosesor: Control & Datapath

  9. Control lines Instruction Decoder PC Address lines MAR IR Memory bus Data lines MDR R0 Y R(n-1) Add ALU control lines Sub ALU XOR Carry-in TEMP Z Organisasi Prosesor (Single-bus) Control Unit DatapathUnit

  10. Siklus Eksekusi Instruksi Eksekusi instruksi yang ukurannya tetap do { 1. IR  M[PC] // Fetch instruksi 2. PC  PC + d // Tunjuk ke lokasi instruksi berikutnya 3. Eksekusi instruksi } while (!stop) Eksekusi instruksi yang ukurannya bervariasi do { do { // Fetch instruksi IR  M[PC] PC  PC + d } while (!end-of-instruction) Eksekusi instruksi } while (!stop)

  11. Operasi-operasi Dasar & Waktu Eksekusi • Operasi-operasi Dasar: • Mengambil (fetching) Data dari Memori • Menyimpan (storing) Data ke Memori • Pertukaran Data Antar-Register • Operasi Aritmatika & Logika di Datapath • Waktu Eksekusi Gate Delay • Waktu yang dibutuhkan output suatu gerbang logika berubah sesuai kondisi inputnya Register’s Delay • Waktu yang dibutuhkan isi register berubah sesuai inputnya

  12. Read MFC Instruction Decoder PC Address lines MAR IR Data lines MDR R1 Y R2 Add Sub ALU XOR Carry-in TEMP Z Mengambil Data dari Memori Instruksi: LD R2,(R1) ; R2  M[R1] Langkah-langkah: • MAR  R1 • Read • Tunggu sinyal MFC// MFC = Memory Function Completed// Pada saat MFC aktif:// MDR  M[MAR] • R2  MDR

  13. Write MFC Instruction Decoder PC Address lines MAR IR Data lines MDR R1 Y R2 Add Sub ALU XOR Carry-in TEMP Z Menyimpan Data ke Memori Instruksi: ST (R1),R2 ; M[R1]  R2 Langkah-langkah: • MAR  R1 • MDR  R2, Write • Tunggu sinyal MFC// MFC = Memory Function Completed// Pada saat MFC aktif:// M[MAR]  MDR

  14. Asynchronous vs. Synchronous Transfer • Asynchronous Transfer: • Transfer data di-inisiasi oleh salah satu peranti (mis. CPU) • Transfer data baru dapat terjadi jika peranti pemilik data (mis. Memori) siap (mis. memberikan sinyal MFC) memasok data • Memungkinkan transfer data antar-peranti dengan kecepatan yang berbeda-beda • Synchronous • Setiap peranti yang bertukaran data mengacu pada 1 clock yang sama • Transfer data berlangsung pada waktu-waktu tertentu mengikuti clock acuan • Implementasi lebih sederhana • Kecepatan transfer ditentukan peranti yang paling lambat

  15. 1 bit line of common bus S Q output:1, 0, open-circuit R _Q 3-state switch Zout Zin Pertukaran Data Antar-Register: Input & Output Gating 1-bit busZinQ X 0 Q 0 1 0 1 1 1 operasi tulis & baca dilakukan secara bergantian memungkinkan peranti lain menggunakan bus Operasi Baca Operasi Tulis ZoutQoutput 0 X 3-state 1 1 1 1 0 0

  16. Pertukaran Data Antar-Register R1in Instruksi: MOV R4,R1 ; R4  R1 Langkah-langkah: • Enable output of R1// setting R1out to 1 • Enable input of R4// setting R4in to 1 X R1 X R1out R4in X R4 X R4out

  17. Riin X Ri X Riout Yin X Y X Yout B A ALU Add X Zin Z X Zout Operasi Aritmatika dan Logika Instruksi: ADD R1,R2 ; R1  R1 + R2 Langkah-langkah: • R1out, Yin • R2out, Add, Zin • Zout, R1in

More Related