1 / 53

CS184a: Computer Architecture (Structure and Organization)

CS184a: Computer Architecture (Structure and Organization). Day 6: January 19, 2005 VLSI Scaling. Today. VLSI Scaling Rules Effects Historical/predicted scaling Variations (cheating) Limits. Why Care?. In this game, we must be able to predict the future Rapid technology advance

courtney
Download Presentation

CS184a: Computer Architecture (Structure and Organization)

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CS184a:Computer Architecture(Structure and Organization) Day 6: January 19, 2005 VLSI Scaling

  2. Today • VLSI Scaling Rules • Effects • Historical/predicted scaling • Variations (cheating) • Limits

  3. Why Care? • In this game, we must be able to predict the future • Rapid technology advance • Reason about changes and trends • re-evaluate prior solutions given technology at time X.

  4. Why Care • Cannot compare against what competitor does today • but what they can do at time you can ship • Careful not to fall off curve • lose out to someone who can stay on curve

  5. Scaling • Premise: features scale “uniformly” • everything gets better in a predictable manner • Parameters: • l (lambda) -- Mead and Conway (class) • S -- Bohr • 1/k -- Dennard

  6. Feature Size l is half the minimum feature size in a VLSI process [minimum feature usually channel width]

  7. Scaling • Channel Length (L) • Channel Width (W) • Oxide Thickness (Tox) • Doping (Na) • Voltage (V)

  8. Scaling • Channel Length (L) l • Channel Width (W) l • Oxide Thickness (Tox) l • Doping (Na) 1/l • Voltage (V) l

  9. Area Capacitance Resistance Threshold (Vth) Current (Id) Gate Delay (tgd) Wire Delay (twire) Power Effects?

  10. l  l/k A = L * W A  A/k2 130nm 90nm 50% area 2x capacity same area Area

  11. Area Perspective

  12. Capacity Scaling from Intel

  13. Capacitance per unit area Cox= eSiO2/Tox ToxTox/k Cox  k Cox Capacitance

  14. Gate Capacitance Cgate= A*Cox A  A/k2 Cox  k Cox Cgate Cgate /k Capacitance

  15. Threshold Voltage

  16. VTHVTH /k Threshold Voltage

  17. Saturation Current Id=(mCOX/2)(W/L)(Vgs-VTH)2 Vgs=VV/k VTHVTH /k WW/k LL/k Cox  k Cox IdId/k Current

  18. tgd=Q/I=(CV)/I VV/k IdId/k CC/k tgd  tgd /k Gate Delay

  19. R=rL/(W*t) WW/k L, t similar R  k R Resistance

  20. twire=RC R -> k R C-> C/k twire -> twire …assuming (logical) wire lengths remain constant... Assume short wire or buffered wire (unbuffered wire ultimately scales as length squared) Wire Delay

  21. Resistive Power P=V*I VV/k IdId/k PP/k2 Power Dissipation (Static Load)

  22. Capacitive (Dis)charging P=(1/2)CV2f VV/k CC/k PP/k3 Increase Frequency? tgd  tgd /k So: f  kf ? P P/k2 Power Dissipation (Dynamic)

  23. Area 1/k2 Capacitance 1/k Resistance k Threshold (Vth) 1/k Current (Id) 1/k Gate Delay (tgd) 1/k Wire Delay (twire) 1 Power 1/k21/k3 Effects?

  24. ITRS Roadmap • Semiconductor Industry rides this scaling curve • Try to predict where industry going • (requirements…self fulfilling prophecy) • http://public.itrs.net

  25. S=0.7 [0.5x per 2 nodes] Pitch Gate MOS Transistor Scaling(1974 to present) [from Andrew Kahng] Source: 2001 ITRS - Exec. Summary, ORTC Figure

  26. Poly • Pitch • Metal • Pitch (Typical MPU/ASIC) (Typical DRAM) Half Pitch (= Pitch/2) Definition [from Andrew Kahng] Source: 2001 ITRS - Exec. Summary, ORTC Figure

  27. 1994 NTRS - .7x/3yrs Log Half-Pitch Actual - .7x/2yrs 0.7x 0.7x Linear Time 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% N N+1 N+2 * CARR(T) = Compound Annual Reduction Rate (@ cycle time period, T) Scaling Calculator + Node Cycle Time: [from Andrew Kahng] Source: 2001 ITRS - Exec. Summary, ORTC Figure

  28. [from Andrew Kahng] Source: 2001 ITRS - Exec. Summary, ORTC Figure

  29. ITRS 2003 Gate/Wire Scaling

  30. What happens to delays? • If delays in gates/switching? • If delays in interconnect? • Logical interconnect lengths?

  31. Delays? • If delays in gates/switching? • Delay reduce with 1/k [l]

  32. Delays • Logical capacities growing • Wirelengths? • No locallity: Lk (slower!) • Rent’s Rule • L  n(p-0.5) • [p>0.5]

  33. Compute Density • Density = compute / (Area * Time) • k3>compute density scaling>k • k3: gates dominate, p<0.5 • k2: moderate p, good fraction of gate delay • [p from Rent’s Rule again – more on Day12] • k: large p (wires dominate area and delay)

  34. Power Density • P-> P/k2 (static, or increase frequency) • P-> P/k3 (dynamic, same freq.) • A -> A/k2 • P/A P/A … or … P/kA

  35. Cheating… • Don’t like some of the implications • High resistance wires • Higher capacitance • Quantum tunnelling • Need for more wiring • Not scale speed fast enough

  36. R=rL/(W*t) WW/k L, t similar R  k R Improving Resistance • Don’t scale t quite as fast. • Decrease r (copper)

  37. Capacitance per unit area Cox= eSiO2/Tox ToxTox/k Cox  k Cox Capacitance and Leakage Reduce Dielectric Constant e (interconnect) or Substitute for scaling Tox (gate quantum tunneling)

  38. Threshold Voltage

  39. ITRS 2003 Table 81a

  40. High-K dielectric Survey Wong/IBM J. of R&D, V46N2/3P133--168

  41. Wire Layers = More Wiring

  42. Typical chip cross-section illustrating hierarchical scaling methodology Passivation Dielectric Wire Etch Stop Layer Via Global (up to 5) Dielectric Capping Layer Copper Conductor with Barrier/Nucleation Layer Intermediate (up to 4) Local (2) Pre Metal Dielectric Tungsten Contact Plug [from Andrew Kahng]

  43. tgd=Q/I=(CV)/I VV/k Id=(mCOX/2)(W/L)(Vgs-VTH)2 IdId/k CC/k tgd  tgd /k Improving Gate Delay Don’t scale V: VV IkI tgdtgd /k2 • Lower C. • Don’t scale V.

  44. Capacitive (Dis)charging P=(1/2)CV2f VV/k CC/k PP/k3 Increase Frequency? f  kf ? P P/k2 …But Power Dissipation (Dynamic) If not scale V, power dissipation not scale.

  45. …AndPower Density • PP(increase frequency) • P> P/k(dynamic, same freq.) • A  A/k2 • P/A  kP/A … or … k2P/A • Power Density Increases …this is where some companies have gotten into trouble…

  46. Physical Limits • Doping? • Features?

  47. Physical Limits • Depended on • bulk effects • doping • current (many electrons) • mean free path in conductor • localized to conductors • Eventually • single electrons, atoms • distances close enough to allow tunneling

  48. What Is A “Red Brick” ? • Red Brick = ITRS Technology Requirement with no known solution • Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment [from Andrew Kahng]

  49. The “Red Brick Wall” - 2001 ITRS vs 1999 Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876 [from Andrew Kahng]

  50. Conventional Scaling • Ends in your lifetime • …perhaps in your first few years after grad school…

More Related