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Fast Statistical Timing Analysis Algorithm for Microelectronic Circuits

This paper presents an innovative algorithm for fast statistical timing analysis of microelectronic circuits, taking into account parameter variations and unpredictable timing behavior. The algorithm provides a more realistic representation of circuit delay and allows for predicting the number of circuits that match the estimated delay. The approach has low calculation effort and can be easily extended to gates with more than two inputs.

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Fast Statistical Timing Analysis Algorithm for Microelectronic Circuits

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  1. Institute of Applied Microelectronics and Computer Engineering Algorithm for Fast Statistical Timing AnalysisJakob Salzmann, Frank Sill, Dirk TimmermannSOC 2007,Nov ‘07, Tampere, Finland University of Rostock

  2. Outline • Motivation • Static Timing Analysis • Statistical Timing Analysis • Simulation Results • Conclusion & Outlook

  3. Motivation(1) • Progressive transistor scaling leads to higher impact of parameter variations • Physical on-chip variations due to • Imprecise fabrication process • Gate oxide thickness • Transistor width, length • Doping • Environment • Ambient temperature • Cooling • Time • Electro migration • Mechanical stress • Thermal stress

  4. I1 I2 Delay Y Time I1 Y I2 I1 I2 Y Time Motivation(2) • Parameter variations lead to unpredictable timing behavior • Chips compete against each other • Before market entry, knowledge about maximum speed in the worst case • Step forward: Information on speed distribution of a chip production set • Most chips are faster than worst case speed! ? Delay ?

  5. I1 I2 Y Worst case delay Time Static Timing Analysis Classic Approach: Worst case analysis • Estimate margins of all parameters • Find parameter set which results in worst case delay • Simulate gate delay with worst case inputs • Add delays of each data path to get resulting delay of the circuit • No realistic representation of timing behavior • Overstated circuit delay

  6. μ – mean value μ σ – standard deviation σ PDF: Statistical Timing Analysis(1) Innovative Approach • Estimate margins and Gaussian distribution of all possible parameters • Monte-Carlo simulations to get delay probabilities • Estimate Probability Density Function (PDF) of gate delay • Calculate PDF of overall delay • More realisticrepresentation of timing behavior • Prediction how many circuits match estimated delay

  7. Statistical Timing Analysis(2) Multi input switching (MIS) Former approach [Aga04] Lot of simulation sets per gate Imprecise calculation of standard deviation #Simulation sets ~ #input² High calculation effort • Single input switching (SIS) • Simple mathematical approach • µY = µ1 + µ2, σY² = σ1² + σ2² • Correlations between gates • Not within scope of this presentation Our new approach Only one simulation set per gate No underestimation ofstandard deviation Simple extension to gates with more than 2 inputs Low calculation effort

  8. Statistical Timing Analysis(3) Multi input switching – Simulation Theses: • Resulting mean value depends on • Gate PDF • Input PDF • Order and time differences of inputs • µYincreases in case of proximate inputs with high standard deviations • µGincreases by proximate inputs • Resulting standard deviation depends on dominating input Difference between Input Mean Values [ps]

  9. I I σY² = σI² + σG² µY = µI + µG Statistical Timing Analysis(4) Approach to calculate proximate effect and dominating input • Separate behavior of gate into impact of Inputs and Gate itself • “Resulting Input PDF“ by convolution of all Input-PDFs • Addition of “Resulting Input PDF“ and ”Gate PDF” by Single Input Switching algorithm

  10. Statistical Timing Analysis(4) Approach for Resulting „Input PDF“ by convolution of all Input-PDFs • Integration of all „Input PDF“ to obtain their Cumulative Density Function (CDF) • Approximation of all „Input CDF“ by a set of linear equations • Multiply the edges of the „Input CDFs“ approximations to get a “Resulting Input CDF“ Mean value by intersection with probability 0.5 Standard deviation by root-mean-square deviation of the points of the “Resulting Input CDF” from mean value

  11. Three example cases HSpice Approximation Case1: σA = 5ps, σB= 10ps Case2: σA= 20ps, σB= 40ps Case3: σA= 40ps, σB= 80ps Simulation Results(1) • Algorithm must not underestimate gatedelay! • Calculated mean value ≥ Simulated mean value • Calculated standard deviation ≥ Simulated standard deviation NAND2 - Gate

  12. I1 I2 I3 ... Y ... I31 I32 Simulation Results(2) • Tree structure – worst case of switching behavior

  13. Conclusion & Outlook • Goal: Developing algorithm for calculating statistical timing behavior of a Multi Input Gate • Only one simulation set per gate • No underestimation ofgate delay • Simple extension to gates with more than 2 inputs • Low calculation effort • Automatic tool for calculating statistical timing behavior of larger (and real) circuits

  14. Questions? Thank you for your attention! References [AGA04] A. Agarwal, F. Dartu, and D. Blaauw; Statistical Gate Delay Model Considering Multiple Input Switching, 41st Design Automation Conference, USA, 2004

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