High-Speed Digital Circuit Design

1. High-Speed Digital Circuit Design • Chris Allen (callen@eecs.ku.edu) • Course website URL people.eecs.ku.edu/~callen/713/EECS713.htm

2. Outline • Syllabus • Instructor information, course description, prerequisites • Textbook, reference books, grading, course outline • Preliminary schedule • Introductions • What to expect • First assignment • Review of circuit fundamentals • When are HSD design techniques needed? • Transient response of reactive circuits • Measuring device reactance • Impact of via inductance • Crosstalk from mutual reactance

3. Syllabus • Prof. Chris Allen • Ph.D. in Electrical Engineering from KU 1984 • 10 years industry experience Sandia National Labs, Albuquerque, NM AlliedSignal, Kansas City Plant, Kansas City, MO • Phone: 785-864-8801 • Email: callen@eecs.ku.edu • Office: 3024 Eaton Hall • Office hours: TR: 10 to 10:50 a.m. • Course description • Basic concepts and techniques in the design and analysis of high-frequency digital and analog circuits. Topics include: transmission lines, ground and power planes, layer stacking, substrate materials, terminations, vias, component issues, clock distribution, cross-talk, filtering and decoupling, shielding, signal launching.

4. Syllabus • Prerequisites • Electronic Circuits I (EECS 312) Non-linear circuit elements, MOSFETs, BJTs, diodes, digital circuits and logic gates • Electromagnetics II (EECS 420) (recommended)transmission line theory • Textbook • High-Speed Digital Design • by H. W. Johnson and M. Graham • PTR Prentice-Hall, 1993, ISBN 0133957241

5. Syllabus • Reference books • High-Speed Digital Propagation – Advanced Black Magic by H. W. Johnson and M. GrahamPrentice Hall PTR , 2003, ISBN 013084408X • High-Speed Digital System Design – A Handbook of Interconnect Theory and Design Practices by S. H. Hall, G. W. Hall, J. A. McCallWiley-IEEE Press, 2000, ISBN 0471360902 • Digital Transmission Lines – Computer Modeling and Analysisby K. D. GranzowOxford University Press, 1998, ISBN 019511292X

6. Grades and course policies • The following factors will be used to arrive at the final course grade: • Homework & quizzes 15 % Design project 15 % Midterm exam 35 % Final exam 35 % • Grades will be assigned to the following scale: • A 90 - 100 % B 80 - 89 % C 70 - 79 % D 60 - 69 % F < 60 % • Note: no +/- grading this semester. These are guaranteed maximum scales and may be revised downward at the instructor's discretion. • Read the policies regarding homework, exams, ethics, and plagiarism.

7. Outline and schedule • Tentative Course Outline (subject to change) • Review of circuits, electronics and traveling wave theory(Thevenin and Norton equivalents, device capacitance and inductance, current sourcing and sinking transmission line impedance, source and load impedance, reflections) • Measurement Issues(requirements and specifications, design for test, test equipment, special fixtures) • Properties of high-speed gates(circuit families and their characteristics, propagation delay, rise/fall times, input impedance, output impedance, sensitivity to electro-static discharge (ESD), heat dissipation) • Transmission lines(microstrip, stripline, coplanar, multiwire) • Ground and power planes(number of planes, placement, characteristics) • Substrate materials(printed wiring boards (PWBs), multi-chip modules (MCMs)) • Thermal issues(junction temperature, thermal resistance, thermal vias, cooling options) • Packaging technologies(packaged parts on PWB (through hole and surface mount), bare die, chip-on-board, multi-chip modules)

8. Outline and schedule • Tentative Course Outline (continued) • Routing issues(fanout limits, stubs, daisy chaining, testability) • Terminations and vias(termination options) • Clock distribution(timing skew, fanout, fine adjustments) • Cross-talk(analysis, design rules, consequences) • Filtering and decoupling(techniques and requirements) • Shielding and grounding(electromagnetic interference (EMI) and electromagnetic compatibility (EMC)) • Signal launching(connection between boards, impedance matching) • Special high-speed circuit design techniques(pipelining and latency, multiplexing) • Future trends(chip speed, complexity, number of I/O, optical interconnection (die and board level), chip stacking)

9. Overview • Many of the topics discussed are covered adequately in the text • Other topics to be discussed will use additional resources including manufacturer’s application notes, product data sheets, and other texts. • High-frequency circuit design is both an art and a science;hence the Black Magic reference in the title. • The text presents general design rules frequently without deriving them;these result from past experience and were learned the hard way. • What is meant by high frequency or high speed?These are relative terms.What we mean is typically signals with fundamental frequency components > 100 MHz although lower frequency signals may qualify in some cases.

10. Applications • Numerous systems use high-speed digital signals.Examples include: • Radar systemsGSa/s analog-to-digital converters (ADCs) and digital-to-analog converters (DACs); systems with wide signal bandwidths; computations measured in GFLOPS • Communication systemschannel rates of 40 Gb/s are common today over long-distance optical fiber • Computerssupercomputers and cluster computing; performance measured in operations per second (OPS); fine-resolution displays • Giga-sample per second: GSa/s • Giga-bit per second: Gb/s • Giga-floating operations per second: GFLOPS

11. Applications • Many of the high-speed digital design techniques apply to both analog and digital signals. Examples include passive component selection and interconnection techniques (e.g., transmission lines), but not active component design. • A major difference is that analog systems often have a bandwidth that is a small fraction of the carrier frequency whereas in digital systems generally require signal frequencies extending from DC to 2 or more times the highest clock frequency. • The key issue is preservation of signal integrity.

12. Outline and schedule • Class Meeting Schedule • August: 27, 29 • September: 3, 5, 10, 12, 17, 19, 24, 26 • October: 1, 3, 8, 10, (no class on15th), 17, 22, 24, 29, 31 • November: 5, 7, 12, 14, 19, 21, 26, (no class on28th) • December: 3, 5, 10, 12 • Final exam scheduled for Monday, Dec 16, 10:30 a.m. to 1:00 p.m.

13. Course website • URL: people.eecs.ku.edu/~callen/713/EECS713.htm • Contains – • Syllabus • Class assignments • Some supplemental course material • Project information (when issued) • Powerpoint files used in class presentations • continually updated to correct errors or enhanced • file contents typically span many presentations (class sessions) • max slide count ~ 100 • Links to recorded presentations (audio and Powerpoint) • Special announcements (when issued)

14. Introductions • Name • Major • Specialty • What you hope to get from of this experience • (Not asking what grade you are aiming for )

15. What to expect • Course is being webcast, therefore … • Most presentation material will be in PowerPoint format  • Presentations will be recorded and archived (for duration of semester) • Not 100% reliable (occasionally recordings fail due to a variety of causes) • Student interaction is encouraged • Remote students must activate microphone before speaking • Please disable microphone when finished • Homework assignments will be posted on website • Electronic homework submission logistics to be worked out • We may have guest lecturers later in the semester • To break the monotony, we’ll take a couple of 1- to 2-minute breaks during each class session (roughly every 15 to 20 min)

16. High-speed digital circuit design

17. Your first assignment • Send me an email (from the account you check most often) • To: callen@eecs.ku.edu • Subject line: Your name – EECS 713 • Tell me a little about yourself and what knowledge you hope to gain from this experience • Attach your ARTS form (or equivalent) • ARTS: Academic Requirements Tracking System • Its basically an unofficial academic record • I use this to get a sense of what academic experiences you’ve had

18. Review • Thevenin and Norton equivalent circuits • Complex circuits can be modeled in terms of VT and ZT (Thevenin) or IN and ZN (Norton)Note that ZT = ZN • This concept applies to both analog and digital devicesboth inputs and outputs • So we can determine the impedance (Z) of a source (driver) or a load

19. Review • Impedances are generally complex: Z = R + jX • R is real part (resistive) • X is reactive part (inductive or capacitive) • Of particular interest is the capacitive nature of the device as this often determines the circuit’s frequency response (time constant) • Another important parameter is the drive device’s current sourcing and sinking capacity (IN) • These (sourcing / sinking) are not necessarily equal depending on the circuit design

20. Review • Transmission lines • Characteristic impedance, Zo = V / I • Velocity of propagation, vp< c • Propagation delay, d = ℓ / vp where ℓ is the line length • Impedance mismatches between the transmission line and the source impedance (ZS) or load impedance (ZL) it connects will reflect part of the impinging wave resulting in distortions in the voltage and current along the transmission line

21. When are HSD design techniques needed? • High-speed design (HSD) techniques (to be explored later) should be applied when the circuit trace length (the line length) ℓ is greater than about a quarter of the length of the rising edge, l • ℓ > l / 4 • Where • and • propagation delay = (propagation velocity)-1

22. When are HSD design techniques needed? • What is rise time ? • Rise time – or fall time (usually assumed to be equal) – can be defined in a variety of methods • Rise time, Tr, is defined as the time required for a signal to change from a specified low value to a specified high value.Typically these values are 10% and 90% of the step height. • Others may use 20% and 80% of the step height or the step height divided by the center or maximum slope(See Appendix B in the text for more details)

23. When are HSD design techniques needed? • Why use rise time, Tr, and not the clock frequency, fCLK? • Consider the circuit • In the time domain the output signal appears as

24. When are HSD design techniques needed? • In the frequency domain the output signal appears as • The knee frequency, Fknee, which is inversely related to the rise time, is much higher than the clock frequency, FCLK. • Most energy in digital pulses concentrates below the knee frequency. • Any circuit with a flat frequency response up to the Fknee frequency will pass a digital signal practically undistorted.

25. When are HSD design techniques needed? • What is propagation delay ? • Signal delay is inversely related to signal velocity • In free space, signals travel at speed of light, vp = cc = 3 x 108 m/s = 30 cm/ns = 11.8 in/ns = 0.0118 in/ps • In free space, delay is Dfreespace = 1/speed = 84.7 ps/in • Propagation through a medium is slower than in free space. • In non-free spacewhere r is the relative permeability andr is the relative permittivity of the medium • Typically, r = 1 so thatwhere n = refractive index = • 1 ns = 10-9 s • 1 ps = 10-12 s • 1 in = 2.54 cm

26. When are HSD design techniques needed? • What is propagation delay ? • Consider a stripline trace in FR-4 (r = 4.5, n = 2.12) • Since the field lines are confined entirely within the glass-epoxy dielectric, the propagation velocity is simply • Trace – A line or "wire" of conductive material such as copper, silver or gold, on the surface of or sandwiched inside a PCB, printed circuit board. • Stripline transmission line geometry • FR-4 – Flame-Retardant industrial laminate having a substrate of woven-glass fabric and resin binder of epoxy. FR-4 is the most common dielectric material used in the construction of PCBs in the USA

27. When are HSD design techniques needed? • What is propagation delay ? • Now consider a microstrip trace on FR-4 • Here the field lines are not confined within the glass-epoxy dielectric, so the effective permittivity is between that of air (r = 1) and that of FR-4 (r = 4.5). • Therefore the propagation velocity is between c and 0.47c. • So for microstrip lines85 ps/in (free space) < D < 180 ps/in (stripline). • Furthermore, the propagation velocity may be frequency dependent leading to signal dispersion and pulse distortion. • Microstrip transmission line geometry

28. When are HSD design techniques needed? • What is l ? • l is the length of the rising edge and l = Tr /D. • Consider a circuit with Tr = 800 ps(GaAs technology) • Fknee for this signal will be (1600 ps)-1 or 625 MHz • The signal propagates on a stripline transmission line fabricated on alumina (r = 8.7). • Find l • So l/4 = 0.8 in or ~ 2 cm • Therefore if the circuit length ℓ > 2 cm HSD design techniques should be followed. • GaAs – An alloy of gallium and arsenic compound (GaAs) that is used as the base material for chips. • Alumina – A ceramic used for insulators in substrates in thin film circuits. It can withstand continuously high temperatures and has a low dielectric loss over a wide frequency range.  Aluminum oxide (Al2O3).

29. When are HSD design techniques needed? • Failure to follow HSD design techniques may result in • Signal reflections Cross talk Interference Ringing

30. Transient response of reactive circuits • Reactances are not usually considered in low-speed digital circuit designs. • Think about low-speed behavior as essentially DC • Reactive circuit elements of interest include:capacitance – load, distributed, parasiticinductance – load, distributed, parasiticmutual capacitance – capacitive couplingmutual inductance – inductive coupling

31. Transient response of reactive circuits • Whatever the nature of the reactance, we can treat it as a lumped quantity being driven by a signal generator. • Consider the circuit loaded by a capacitor, driven by a step function. • Predict the resulting output voltage (Vo(t)), current (I), and short-term impedance (i.e., Vo(t)/I(t)) as the circuit responds to the stimulus. • What will the output voltage be immediately after the step function? • What will be the steady-state output voltage? • What will the current be immediately after the step function? • What will be the steady-state current?

32. Transient response of reactive circuits • Time-domain viewpoint • Capacitor voltage cannot change instantaneously • Over short-time intervals capacitors behave as ideal voltage sources. • For modeling purposes, capacitors are modeled as a short circuits. • Long after the transient, the capacitor current goes to zero • For modeling purposes, capacitors are modeled as open circuits. • Inductor current cannot change instantaneously • Over short-time intervals an inductor behaves as a current source. • For modeling purposes, inductors are modeled as open circuits. • Long after the transient, the inductor voltage goes to zero • For modeling purposes, inductors are modeled as short circuits. • Frequency-domain viewpoint • At high frequencies, capacitors behave as shorts, inductors as opens • At low frequencies, capacitors behave as opens, inductors as shorts

33. Transient response of reactive circuits • Transient response to step function.

34. Transient response of reactive circuits • Consider the circuit loaded by a perfect inductor, driven by a step function. • Predict the resulting output voltage (Vo(t)), current (I), and short-term impedance (i.e., Vo(t)/I(t)) as the circuit responds to the stimulus. • What will the output voltage be immediately after the step function? • What will be the steady-state output voltage? • What will the current be immediately after the step function? • What will be the steady-state current?

35. Transient response of reactive circuits • Transient response to step function.

36. Transient response of reactive circuits • Homework #1 • Following a similar procedure, predict the transient response for the four load conditions shown. • See the course website for homework assignment details.

37. Measuring device reactance • Sometimes is it necessary to measure reactance (capacitance & inductance) of devices • circuit structures (traces) • packages • leaded components • Why not apply EM analysis instead ? • too many unknowns (r, internal geometry, material ) • complex geometries, difficult to measure or model • cost in $, time, resources • Building a small test fixture may be • more efficient and accurate • relatively simple to fabricate

38. Measuring device reactance • Test equipment requirements • While specialized test equipment exists to characterize inductance, capacitance, resistance, etc., such instruments may not be available. • More common instrumentation that may be used include • Pulse generator with a small Tr value • Oscilloscope with a wide bandwidth • see page 85 in text • BW3dB – bandwidth over which signal power falls by 50% (3 dB)

39. Measuring device capacitance • Capacitance test fixture design • Simplified test circuit • Thevenin equivalent circuit connected to unknown capacitive load, Z, also known as the Device Under Test (DUT) • The output voltage from simple, first-order RC circuit is • where  is the circuit’s time constant,  = Rs C. • If Rs is known, the unknown capacitance, C, can be estimated by observing the rise time  of Vo

40. Measuring device capacitance • If the anticipated DUT capacitance is a few pF, what value of Rs is required to provide a measurable  ? • Example:assume pulse generator’s Tr= 800 ps (BW = 0.35/800 ps = 440 MHz)assume oscilloscope’s BW 440 MHzoscilloscope’s smallest useful time scale ~ 500 ps / divtherefore we need   500 ps • If we assume C = 1 pF and set  = 500 ps, thenRs =  / C  500 ps / 1 pF orRs  500 

41. Measuring device capacitance • Suggested capacitance test fixture design • Determine values for R1andR2 so that Rs 500 

42. Measuring device capacitance • Capacitance test fixture design insights • To reduce reflection which would corrupt the measurement –the cables have Zo = 50 the oscilloscope has internal termination of 50 the test fixture has termination of 50 the pulse generator has source termination of 50  • Coaxial cables enter/exit from opposite sides to reduce direct feed-through • R1 provides isolation between the source and the DUT • R2 acts as a voltage divider with the oscilloscope’s 50- termination

43. Measuring device capacitance • Suggested value for R2 is 1000  (1 k) • This keeps the scope from loading the capacitor, i.e., without R2, Rs~ 50  • For R2 = 1000 , what should R1 be to make Rs  500  ?To answer this, analyze the circuit as seen by the DUT

44. Measuring device capacitance • The resistance between the DUT terminals written asRs = (1000 + 50) // (R1 + 50 // 50)  500  orRs = (1050) // (25 + R1)  500  or1/1050 + 1/(25 + R1)  1/500 orR1  930  • With 5% resistorschoices are910  or 1000  • ThereforeR1 = 1000 andRs = 519 

45. Measuring device capacitance • We can test our setup by shorting the DUT test points • ideal response should be zero • Circuit analysis needed to • predict the range of Vo • select the power rating for resistors • using steady-state analysis when V = 1 V

46. Measuring device capacitance • In steady state, treat DUT as open circuit • Resistance seen by sourceR = 50 + 50//2050 orR = 98.8  • Source current, I1, isI1 = 1 V / 98.8 I1 = 10.1 mA • Node voltages and branch currents areVA = 1 – (50) (I1) = 494 mVI2 = 494 mV / 50 = 9.88 mAI3 = VA / 2050 = 241 AVB = (1050) (I3) = 253 mVVC = 12 mV • Note that VB/VC = 21a 21:1 voltage reduction

47. Measuring device capacitance • Capacitance test fixture design • Now find the power dissipation in various resistorsIn the pulse generator’s Rs, Pdiss = RS(I1)2 = 5 mWIn the test fixture’s 1-k resistors, Pdiss = 1k(I3)2 = 58 WIn the test fixture’s 50- resistor, Pdiss = 50(I2)2 = 5 mW • Therefore 1/8-W resistors can be used in the test fixture

48. Measuring device capacitance • Capacitance test fixture application • The Thevenin equivalent circuit for this test fixture is • With the a component in the DUT, find the rise time when t = , Vo = Vs(1 – e-1) = 63.2% of Vs orVo = 160 mV and Vmeas = 7.58 mV •  corresponds to the point where ΔV = 7.58 mVC =  / 519  • For example: If = 15 ns,then C = 29 pF • Vmeas = Vo / 21

49. Measuring device inductance • Similar to the discussion on capacitance measurement, we can design a fixture for measuring device inductance. • Setup designed to measure inductances as low as a few nH. • Thevenin equivalent circuit connected to unknown inductive load, Z, also known as the Device Under Test (DUT). • We know that the current through an inductor cannot change instantaneously, andwhere the time constant,  = L/Rs • For L = 1 nH (10-9 H) and a desired  of 500 psrequires Rs~ 2  (i.e., a small Rs value is desired)

50. Measuring device capacitance • Suggested inductance test fixture design • Determine values for R1andR2 so that Rs< 2 