Implementation of high speed digital channel

1. Implementation of high speed digital channel High Speed Digital System Lab Spring 2009 1 semester project Instructor: MonyOrbach Students: Pavel Shpilberg OhadFundoianu

2. Topics • Introduction • Project targets • Block diagram • Stratix 2 transmitter • Stratix 2 reciever • Work environment • Changeable parameters • Time table

3. Introduction • As technology have gotten faster, the demand for higher data transfer rates between devices has grown. • It turns out that the serial communication provides better solution, than the parallel one. • A known serial high speed communication protocol is PCI-Express.

4. Project targets • Implementation of high speed digital channel • Examining Stratix card ability of GX (protocols and parameters). • Testing the channel by checking the distortion of signals along the lines. • Learning and understanding the physical part of high speed channels.

5. Block diagram Encoding Serilizer 8 8 input 2 Decoding Deserilizer 8 8 PLL output • Channel: • rate: up to 6.375 Gbps

6. Stratix 2 transmitter m m Phase compensation Byte serializer * m 1 n Serializer 8B/10B Encoder* PLL

7. Stratix 2 reciever 1 1 n Deserializer Word Aligner PLL+CRU n m m n m Phase compensation Byte Deserializer * 8B/10B Decoder * Rate matcher *

8. Work enviroment • The channel will be implemented using Stratix 2 GX card. Working tools: • Quartus 2 – Design and programming in VHDL. • Hyperlinx – Simulation of transmissions lines.

9. Changeable parameters • Serial channel rate: 600[Mbps]-6.375[Gbps] • PLL ref. clock rates 50-622.08[MHz] • Varies types of functional modes : PCIE, SONET/SDH, GIGE, Basic, XAUI. • Receiver termination (100,120,150) • Pre-emphasis and equalization • 8B/10B coding • Rate matcher • Byte deserializer

10. Time table