Get ‘O Scope The PC Oscilloscope for Budding Engineers

1. Get ‘O ScopeThe PC Oscilloscope for Budding Engineers ECE 445 - Group 25 Abe Rozental, Luke Lempart, & Paul Ferrara April 26, 2006

2. KErpoW!!!

3. Get ‘O Guts

4. Introduction • Inexpensive oscilloscope for: • College Students • Basement Hackers • Classrooms • Professional Engineers • Easy to build, maintain, upgrade, and study

5. Design Parameters • PC Based – Eliminates need for screen and other expensive hardware • USB Interface – 10MHz/20MHz theoretical bandwidth, no external power • 2 Channel • Alias Detection • Custom Software – Allows upgrades for analysis tools (i.e. RS232)

6. Design Parameters – 2 • 24 Vpp Input with Prescaler – 2, 4, 8, and 12 volt prescale • >1MΩ Impedance • Voltage Overload Protection • Auto Cursors – Pk-Pk, Amplitude, RMS, Period

7. δSpec/δt • 83/200KHz Bandwidth • Meets all other design parameters

8. Software Interface

9. Cursors Drag & Drop Cursors Inline Cursor Difference Cursor Projection

10. UI Controls Time Scale Triggering Auto Cursors Stop/Start Vertical Scale Alias Indicator Interpolation Channel On/Off

11. Hardware Controls Bunny Ears Channel Select Standard BNC Connector Prescaler Knob Alias Detector

12. Hardware Layout Divider Logic High Z Prescaler 10-bit ADC FTDI USB PIC 18F458 Alias Detector

13. Hardware - Overview

14. Hardware - ADC • National ADC10464 • 1.6M S/s • 10-bit samples • Onboard 4 channel analog mux • Samples clocked from PIC

15. Hardware – High Z Prescaler • 1:2, 1:4, 1:8, 1:12 analog voltage divider • +/- 4V postscale clamp Design Challenge • At high frequency, resistor leads model as inductors – cause improper division • Solution: Parallel analog and DC dividers

16. Hardware – High Z Prescaler - 2

17. Hardware – Prescaler Tests 4Vpp Divider Circuit – 150kHz Input Frequency 4Vpp Divider Circuit - 150Hz Input Frequency INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 970mV SCALE: 2.06 INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 770mV SCALE: 2.59 8Vpp Divider Circuit - 150Hz Input Frequency 8Vpp Divider Circuit – 150kHz Input Frequency INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 410mV SCALE: 4.88 INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 500mV SCALE: 4.00

18. Hardware – Prescaler Test - 2 16Vpp Divider Circuit - 150Hz Input Frequency 16Vpp Divider Circuit - 150kHz Input Frequency INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 250mV SCALE: 8.00 INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 184mV SCALE: 10.86 24Vpp Divider Circuit - 150Hz Input Frequency 24Vpp Divider Circuit - 150kHz Input Frequency INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 128mV SCALE: 15.62 INPUT VOLTAGE: 2Vpp DIVIDER OUTPUT: 172mV SCALE: 11.63

19. Hardware – Voltage Clamp Tests Voltage Clamp with 4Vpp Divider Circuit - 150Hz Input Frequency Voltage Clamp with 4Vpp Divider Circuit - 150kHz Input Frequency INPUT VOLTAGE: 2Vpp CLAMP OUTPUT: 800mV SCALE: 2.50 INPUT VOLTAGE: 2Vpp CLAMP OUTPUT: 970mV SCALE: 2.06 Voltage Clamp with 4Vpp Divider Circuit - 150Hz Input Frequency Voltage Clamp with 4Vpp Divider Circuit – 150kHz Frequency INPUT VOLTAGE: 20Vpp DIVIDER OUTPUT: 6.2V SCALE: NA INPUT VOLTAGE: 20Vpp DIVIDER OUTPUT: 2.86V SCALE: NA

20. Hardware – Alias Detection • Allows end user to see if they are sampling a wave out of spec without rendering scope useless • Schmitt Trigger lights physical LEDs • Difference amp provides logic ‘1’ and ‘0’ for PC • Accurate to within 50Hz

21. Hardware – Alias Detection - 2

22. Hardware – Alias Detection Test INPUT FREQ. = 100 kHz - Alias Logic Voltage (CH2) @ 2.38V (Logic 1) INPUT FREQ. = 250kHz - Alias Logic Voltage (CH2) @ 0.71V (Logic 0)

23. Hardware Design - USB • 1st USB Interface Failed • FTDI USB->Serial Converter w/Parallel load FIFO • 8 Mbps max speed • Problem: Upload delay every 4KB • Solution: Does not exist

24. Hardware Design – USB - 2 FTDI chip cannot stream data – lags during 4KB upload

25. PIC Firmware • PIC18F458 • Clocked at 40 MHz, 4.5 I/O ports • Limiting reagent for bandwidth • 10 Mips max for PIC18 series • 25 (30) instructions for single 1CH (2CH) sample • Limitations • Must wait for TXE# to perform next write • Must wait for INT# before reading samples

26. PIC Firmware (continues) • Set up ports and turn off PIC features • Wait for instructions • Need start byte • Others optional • Loop collecting samples • 2 modes • 1 CH and 2 Ch • Only difference is switching CH_SEL • Separate code segments to increase 1 CH BW

27. PIC Firmware (continued) • If TXE# high for extended period of time • Stop transmission • Process any awaiting instructions • Switch number of channels • Send hardware/firmware version info (debugging purposes) • Wait for TXE# low

28. PIC Testing • Used MPLAB SIM • Not very useful • Stimulus generator not fun at all • Countless hours with logic analyzer • Make sure logic triggered at correct moments • Optimized code by observing behavior of both the ADC and USBMOD2 • Timing diagram on next slide

29. PIC – Timing Diagram

30. Back to the Future • 10/20MHz bandwidth • Change USB interface to 480Mbps • Faster ADC • Faster sample->USB path • High-Z input with op amps • Find high frequency unity gain stable op amps

31. Back to the Future - 2 • Software • More auto cursors • Collapsible UI (to view more of the wave) • SINC interpolation • Virtual channels • PC Based Logic Analyzer

32. Thanks To • Professor Carney • Austin Kirchhoff • Analog Devices • http://hyperphysics.phy-astr.gsu.edu/HBASE/electronic/schmitt.html • http://www.emcesd.com/1ghzprob.htm (No probes were harmed in the making of this presentation)