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This study by Lodovico Ratti from Università di Pavia and INFN focuses on estimating the area for a 10-bit DAC in a SAR ADC. Various passive components like resistors and capacitors are analyzed in terms of sizes, sheet resistance, and capacitance to determine the optimal design for power dissipation and accuracy. The text explores different approaches, such as R-2R ladder, capacitive dividers, and hybrid capacitive-resistive DAC, considering factors like total area and characteristic behavior. The study also delves into the necessity of 10-bit resolution in SAR ADCs, proposing considerations for signal measurement accuracy and noise margins. Further insights from recent literature reveal the proximity of the research to state-of-the-art advancements, highlighting challenges in power dissipation, area constraints, and the prevalent use of capacitive networks in DACs. The discussion questions the practicality of 10-bit resolution in certain scenarios, suggesting alternatives for improved spatial resolution and noise management.
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Rough estimation of the area for a 10 bit DAC in a SAR ADC Lodovico Ratti Università di Pavia and INFN Pavia PixFEL phone meeting, Pavia, June 5th 2013
Passive components Resistors n-type poly: min size: 400 nm x 400 nm sheet res: 14.3 Ohm/square n-well on active area: min size: 1.8 um x 9 um sheet res: 336.1 Ohm/square Capacitors MIM: min size: 2 um x 2 um capacitance: 2.4 fF/um2
R-2R ladder • no of unit elements Ru: 3n • hypothesis: use n-well resistors (not minimum dimensions) and assume Ru>10 kOhm (for power dissipation) • Au=2 um x 60 um • Total area > 3600 um2 • not so small area, non monotonic characteristic
Capacitive divider • no of unit elements Cu: 2n • hypothesis: Cu=~20 fF • Au=9 um2 • Total area > 9200 um2 • too large area
Capacitive divider with attenuator • no of unit elements Cu: 2n/2 • hypothesis: Cu=~20 fF • Au=9 um2 • Total area > 300 um2 • CA is critical
Hybrid capacitive-resistive DAC • m MSB (resistive), n-m LSB (capacitive) • no of unit elements Ru: 2m • no of unit elements Cu: 2n-m • hypothesis: use n-well resistors (not minimum dimensions) and assume Ru>10 kOhm/2m (for power dissipation) • case of m=3, n=10 • A(Ru)=2 um x 8 um • Total resistive area =128 um2 • A(Cu)=9 um2 • Total capacitive area=1152 um2 • Total area=1280 um2 • accuracy in the resistive divider may be critical for n>8
ADC specifications We are thinkingabout a SAR ADC with the followingspecifications • resolution: 10 bits • sampling rate: 5 MS/s • powerdissipation < 200 uW • area: < 5000 um2 • fabricationprocess: CMOS 65 nm From a quickreview of the mostrecentliterature (seeexceldocument) on the subject, itseemswe are prettyclose to the state of the art • only a fewworks with powerdissipationnotexceeding 100 uW (notsureaboutthem, averagepowerdissipationisaround 1 mW) • only a fewADCs with area below 5000 um2 • most, ifnotall, use capacitive networks in the DAC
About the resolution specification Are 10 bits reallynecessary/useful? For large number of photons, measurementaccuracyislimited by Poissonnoise, whichgoeslike the sqrt(no. of photons); therefore • single photonresolutionmakessense for signalsnotexceeding a fewtens of photons • at large signals, alsodepending on the non linear, compressionfeatures of the front-end channel, 10 bits might be an overkill Thereis of course some advantage in using more thanone bin per photonat small signals largernoisemargins One can think of using more than a single bin also to improvespatialresolutionthroguhamplitudemeasurement (in the case of chargesharingbetweenadjacentpixels, likelyathv>1keV)
