An Emerging Computing Model: A Network of Four-terminal Switches

1. An Emerging Computing Model: A Network of Four-terminal Switches Mustafa Altun Electrical & Computer Engineering University of Minnesota Advisor: Marc D. Riedel

2. Switch-based Boolean computation Shannon’s work: A Symbolic Analysis of Relay and Switching Circuits(1938)

3. Two-terminal and four-terminal switches

4. A lattice of four-terminal switches 3 × 3 2D switching network and its lattice form

5. Motivation Regular arrays Regularity; ease of design. Nanotechnology Self-assembled systems. Self-assembled circuit with 64,000 elements in three minutes Self-assembled nanowires

6. Motivation Crossbar array of four-terminal switches Technology independent! Nanowire four-termial switch Spin-wave four-termial switch

7. Outline Logicsynthesis for lattices of four-terminal switches. Defect tolerance for lattices of four-terminal switches. Mathematics of lattice-based computation: self-duality problem. Future Work

8. Outline Logicsynthesis for lattices of four-terminal switches. Defect tolerance for lattices of four-terminal switches. Mathematics of lattice-based computation: self-duality problem. Future Work

9. Boolean functionality and paths Switches are controlled by Boolean literals. fLevaluates to1iff there exists a top-to-bottom path. gLevaluates to1iff there exists a left-to-right path.

10. Logic synthesis problem How can we implement a given target Boolean function fTwith a lattice of four-terminal switches? Example:fT= x1x2x3+x1x4

11. Logic synthesis problem Example:fT= x1x2x3+x1x4+x1x5 9 TOP-TO-BOTTOM PATHS!

12. Our synthesis method Example:fT= x1x2x3+x1x4+x1x5 fTD= (x1+x2+x3)(x1+x4)(x1+x5) fTD= x1 + x2x4x5 + x3x4x5 • Start with fTandits dual. • Assign each product of fT to a column. • Assign each product of fT D to a row. • Compute an intersection set for each site. • Arbitrarily select a literal from an intersection set and assign it to the corresponding site.

13. Our synthesis method

14. Math behind the method – Theorem 1 Theorem 1(Altun and Riedel, 2010): If fT and fTD are implemented as subsets of all top-to-bottom and left-to-right paths, respectively, thenfL=fTand gL=fTD.

15. Math behind the method – Theorem 1 Theorem 1 allows us to only consider column-paths.We do not need to enumerate all paths!

16. Math behind the method – Theorem 2 Lemma (Fredman and Khachiyan, 1996): Consider products Pi and PjoffT and fTD in ISOP forms, respectively. Pi ∩ Pj ≠ Ø Theorem 2 (Altun and Riedel, 2010):Consider a product Pi of fT in ISOP form. For any literal x of Pi there exists at least one product Pj of fTD such that Pi ∩ Pj = x.

17. Math behind the method – Theorem 2 Theorem 2 (Altun and Riedel, 2010):Consider a product Pi of fT in ISOP form. For any literal x of Pi there exists at least one product Pj of fTD such that Pi ∩ Pj = x. Each column is for each product!

18. Our method’s performance The time complexity: O(m2n2) Size of the lattice:m×n n and m are the number of products of the target function fT and its dual fTD, respectively.

19. Implementing parity functions A Parity functionfevaluates to 1 iff the number of variables assigned to 1 is an odd number:

20. Implementing parity functions

21. Implementing parity functions Lattice size: (logm +1)×n compared tom×n n and m are the number of products of the target function fT and its dual fTD, respectively.

22. A lower bound on the lattice size Circuit complexity Lower bound

23. An inspiring example • What are the lower bounds for the target functions? • For both functions the lattice size of our method is n×m = 3×3 = 9. • Is it optimal? • YES for fT1; NO for fT2.

24. An inspiring example • We need at least 3 rows to implement the target functions. • Can we implement the target functions with 2 columns? • NO for fT1; YES for fT2. • The minimum lattice sizes for fT1and fT2 are 9 and 6.

25. Deriving the lower bound • The lower bound is derived from two variables v and y. v:The maximum number of literals in a product of the target function fT in ISOP form. y:The maximum number of literals in a product of the target function’s dual fTD in ISOP form.

26. Deriving the lower bound vT1=3 vT2=3; yT1=3 yT2=2 yT1> yT2

27. Deriving the lower bound R and C are the numbers of rows and columns of the lattice that implements fT, respectively.

28. The lower bound numbers The lattice size R×Cfor differentvand yvalues

29. Experimental results

30. Outline Logic synthesis for lattices of four-terminal switches. Defect tolerance for lattices of four-terminal switches. Mathematics of lattice-based computation: self-duality problem. Future Work

31. Computing with Defects • OFF-to-ON defect: The switch is ON when it is supposed to be OFF; x1=0. • ON-to-OFF defect: The switch is OFF when it is supposed to be ON; x1=1. • Each switch of the lattice has independent defect rates. 31 31

32. Computing with Defects • Ideally, if x1=0 then all the switches are OFF. • Ideally, if x1=1 then all the switches are ON. • We use redundancy in tolerating defects powered by percolation. 32 32

33. Percolation Theory Rich mathematical topic that forms the basis of explanations of physical phenomena such as diffusion and phase changes in materials. Broadbent & Hammersley (1957). 33

34. Percolation Theory Sharp non-linearity in global connectivity as a function of random local connectivity. 34

35. Percolation Theory p2versusp1for 1×1, 2×2, 6×6, 24×24, 120×120, and infinite size lattices. • Each square in the lattice is colored black with independent probabilityp1. • p2is the probability that a connected path exists between the top and bottom plates. 35 35

36. Margins • One-margin: Tolerable p1ranges for which we interpret p2 as logical one. • Zero-margin: Tolerable p1 ranges for which we interpret p2 as logical zero. Margins correlate with the degree of defect tolerance. 36 36

37. Implementing Boolean functions signals in: xi’s signals out: connectivity top-to-bottom / left-to-right. 37 37

38. An example with 16 Boolean inputs A path exists between top and bottom, fL = 1 38 38

39. Margin performance with a 2×2 lattice fL=x1x3+x2x4 gL=x1x2+x3x4 Different assignments of input variables to the regions of the network affect the margins. 39 39

40. One-margins (always good) ONE-MARGIN fL=0 fL=1 Defect probabilities exceeding the one-margin would likely cause an (1→0) error. 40 40

41. Good zero-margins ZERO-MARGIN fL=0 fL=1 Defect probabilities exceeding zero-margin would likely cause an (0→1) error. 41 41

42. Poor zero-margins POOR ZERO-MARGIN fL=1 fL=0 Assignments that evaluate to 0 but have diagonally adjacent assignments of blocks of 1's result in poor zero-margins 42 42

43. Lattice duality A necessary and sufficient condition for good error margins is that the Boolean functions fLand gLare dual functions. 43

44. Lattice duality fL=x1x3+x2x4 gL=x1x2+x3x4 fL ≠ gLD 44

45. Optimization problem • For a given target Boolean function fThow tooptimize of the lattice area (R×C×N×M) while meeting prescribed defect tolerances? • Determine R×C; determine N×M. 45

46. Optimization problem The Algorithm Begin with the target function fT and its dual fTD Find a lattice with the smallest number of regions that satisfies the conditions: fL = fT and gL = fTD. This determines R×C. Dependent on the defect rates of the technology, determine the required one and zero margin values. Determine the number of switches required in each region in order to meet the prescribed margins. This determines N×M.

47. Experimental results Required lattice areas for the target functions meeting 10% one and zero margins.

48. Outline Logic synthesis for lattices of four-terminal switches. Defect tolerance for lattices of four-terminal switches. Mathematics of lattice-based computation: self-duality problem. Future Work

49. Boolean duality • Famous unsolved problem (self-duality problem): • Time complexity of testing whether a monotone Boolean function in IDNF is self-dual. Monotone: No negation IDNF: Irredundant form Self-dual:

50. Boolean duality Consider a monotone self-dual Boolean function f in IDNF with k variables and n disjuncts: Lemma (Fredman and Khachiyan, 1996; Gaur and Krishnamurti, 2008):k ≤ n2.. Theorem(Altun and Riedel, 2012):k ≤ n.