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FPGA PID DC Motor Controller by Galt Design

Implement PID control of DC Motor through PWM pulsing of H-Bridge with input from Quadrature decoder for position information. Features PID, deadband, integrator limit, and ramping settings. Available in Verilog and VHDL for FPGA and ASIC designs, includes DC Motor timeout detector.

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FPGA PID DC Motor Controller by Galt Design

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  1. FPGA PID DC Motor ControllerGalt Design, Inc.

  2. Short Description • PID control of DC Motor through PWM pulsing of H_Bridge • Takes input from Quadrature decoder for position information • PID, deadband, integrator_limit,ramping, timeout settings available • Available in both Verilog and VHDL HDL code • Can be used in both FPGA and ASIC designs • DC Motor Timeout detector. Shuts down drive if motor jams.

  3. PID Thermal controller FPGA PID motor controller FPGA Example Done Interrupt Requested position, parameters CPU interface PID DC Motor Controller 1 DC_motor H-Bridge 2 32 Quadrature counter Quadrature

  4. Accumulator * * *  Quadrature Encoder Input PID Motor Control Diagram Derivative Gain Register D term Temperature Setpoint Register Integral Gain Register Positive or Negative PWM pulses to DC Motor H-bridge - I term Error P term Proportional Gain Register

  5. Example FPGA Code Organization Quadrature_decoder.v dc_motor_control.v Pid_controller.v Dc_motor_timeout.v

  6. Contact information • Contact us with questions or for a quote: • pid@galtdesign.com

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