8086 Hardware Specifications

1. 8086 Hardware Specifications

2. 8086 Pinout (40 pins) in minimum mode MN/MX’ (33) VCC (40) GND (1, 20) CLK (19) AD0 – AD15 ALE (25) A16/S3 – A19/S6 RD’ / WR’ (32, 29) M/IO’ (28) RESET (21) NMI (17) INTR (18) DT/R’ DEN’

3. Instruction Execution

4. Instruction Cycle Machine Cycle T states

5. CLK is crystal controlled clock sent to 8086 from an external clock generator device such as 8284. • One cycle of this clock is called a state. • A state is measured as falling edge of one clock pulse to falling edge of next clock pulse. • Different versions of 8086 have maximum clock frequencies of between 5MHz and 10MHz, so the minimum time of one state will be between 100nS to 200nS. • A basic operation such as reading a byte from memory or writing a byte to a memory or port is called a machine cycle.

6. Memory Read Machine Cycle

7. In Read Machine Cycle: During T1 asserts DT/R signal low to put data buffers in receive mode. ( why buffers needed?) When 8086 finishes using the data bus to send address ( lower 16 bits), it asserts DEN low to enable the data bus buffers Data put on the data bus by an addressed port or memory will then be able to come in through the buffers to 8086 on the data bus.

10. ADDRESS and DATA being MULTIPLEXED on the ADDRESS BUS A0 – A15. AD0 – AD15 Demultiplexed externally using latch.

11. 74373 8-bit Latch