LAL/LPNHE work for the AIDA WP3

1. LAL/LPNHE work for the AIDA WP3 A. Lounis, G. Martin-Chassard, D. Thienpont, J. Tongbong (LAL) G. Calderini, F. Crescioli, J-F. Genat, O. Le Dortz (LPNHE) June 26, 2013

2. Interconnection project at LAL/LPNHE • Readout ASICs in 3D or 65nm technology interconnected using the CEA-LETI , EMFT or IPDIA process. The wafers need to be post-processed (thinning, etching of vias and addition of a redistribution layer).

3. LAL/LPNHE project status • 3D (GF/Tezzaron) OMEGAPIX2 chip delayed • Submitted in October 2011. The latest news, the wafers were manufactured by GF and were shipped to Tezzaron. From two to three weeks are required for the 3D assembly, but Tezzaron do not tell us when it starts ... • MOSIS promises to sent us 2D circuits. But we have nothing received yet. • A new OMEGAPIX chip in 65 nm techno as an alternative to the 3D chip • Same pixel form factor: 35x200 μm • New analog front-end (LAL), new digital pixel (LPNHE) • TSMC 65 nm techno (by Europractice) • 3x1z1u metal stack (RF, CRN65LP), 6 metal layers + RDL • tcbn65lp standard cells library • In waiting for the common PDK provided by CERN

4. Analog front-end • A very classical architecture with preamp, shaper and comparator is designed Threshold 3 bits global Cmim Gain = 1.5 Gain = 65 mV/fC Cf = 15 fF Nmos_na Leakage I absorption ToT tuning (global or local) Vref + local DAC (5 bits)

5. Analog front-end

6. Simulations performances • Typical Low Power transistor • Cf = 15 fF => 66 mV/fC • with Cd = 300 fF, ENC from 80 e- to 120e- when leakage current varies from 0 to 100 nA • Preamp Open Loop gain = 90 dB • Global power consumption: vdd = 1.2 V and I = 8 μA => 9.6 μW • Dynamic range: 450 mV max. • Local 5-bit DAC • Low power => relatively high resistor value in each pixel 6

7. General considerations • Capa • No poly capacitor • MIM capacitor: large area reserved around • Monte Carlo simulations • we are not able to make MC simulations: there are many sections in Spectre models and traditional mc section does not work as usual

8. Pixel readout (LAL LPNHE) Pixels readout : Two options -1 In-pixel circular buffer -2 Use in-pixel storage (FIFOs) instead of circular buffer to reduce power and Silicon area • Hit times are recorded for the L1 latency • At L1, hit times in FIFOs are compared to the current time and • selected for L2 if hit time matches L1 time

9. Circular buffer scheme Selective readout scheme Pixel hit Pixel hit Current time (8-bit) Circular buffer vs on-pixel FIFOs 120-deep Circular Memory Dynamic Memory Use the same Dynamic Memory Cell Beam Crossing Pixel FIFO depth 16 Goal: Save silicon area and power at the pixel level Current time - 120 L1 Trigger L1 Trigger Readout Readout

10. Extract a stack of addresses of pixels hit in time with L1 Timing based pixels sparse scan readout - A pixel switch is open on a hit - At L1, each read clock cycle outputs the address of a pixel with a hit time matching this L1, from top to bottom - The read pixel switch is closed after read - The next hit pixel (switch open) is read

11. Example: FIFO Based Pixel Matrix Readout Sparse scan columns in parallel Sparse end of columns readout Readout time is (clock period x number of hit pixels) only

12. VHDL code synthesizedusing the TSMC as well as custom librariese.g. 35 x 60 mm2 for a 16-deep FIFO 65nm Timing based readout simulation

13. Layout size in 65nm TSMC and custom libraries 70um FIFO depth 24 35um

14. Buiding blocks in 65 nm: PLL and analogue buffer Done by Jeanne Tongbong • PLL • Fast lock and tracking • Fully integrated • Low power and jitter • OTA buffer • Rail-to-rail • schrink of an OTA designed in 130 nm Kvco = 467Mhz/V Kvco = 1300Mhz/V Analogue VCO Digital VCO with 11 delay cells

15. Status • We have installed the 65 nm PDK of TSMC • Provided by Europractice • First preliminary design: analogue (LAL) and digital (LPNHE) • PLL and analogue buffer preliminary design • Waiting for the 65nm kit from CERN • 3D: Omegapix2 not yet received. Expected delivery at the end of the summer