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Pipeline Demo CONTROL

Pipeline Demo CONTROL. WB. WB. M. M. ADD. EX. ADD. ZERO. ALU. RESULT. PC. INSTRUCTION MEMORY. ADDRESS. INSTRUCTION. 1. MUX. 0. 0. MUX. 1. MIPS: 5-Stage Pipeline. PCSrc. EX/MEM. MEM/WB. ID/EX. WB. 0. RegWrite. MemToReg. MUX. CONTROL. Branch. 1. MemRead. MemWrite.

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Pipeline Demo CONTROL

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  1. Pipeline DemoCONTROL

  2. WB WB M M ADD EX ADD ZERO ALU RESULT PC INSTRUCTION MEMORY ADDRESS INSTRUCTION 1 MUX 0 0 MUX 1 MIPS: 5-Stage Pipeline PCSrc EX/MEM MEM/WB ID/EX WB 0 RegWrite MemToReg MUX CONTROL Branch 1 MemRead MemWrite RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS READ DATA 1 READ REGISTER 1 / READ DATA 2 READ REGISTER 2 0 DATA MEMORY ADDRESS READ DATA MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[15-0] I[5-0] RegDst I[20-16] ALUOp I[15-11]

  3. ADD PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg PC MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1 Stage 1: Instruction Fetch

  4. PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ADD Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1 Stage 2: Instruction Decode (and Register Fetch)

  5. ADD ZERO ALU RESULT 0 MUX 1 Stage 3: Execute (or ALU Operation) PCSrc MEM/WB EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc ADD Branch RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION READ DATA 2 READ REGISTER 2 0 DATA MEMORY 1 ADDRESS READ DATA MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[5-0] RegDst I[20-16] ALUOp I[15-11]

  6. 0 MUX 1 Stage 4: Memory Access (and Branch Resolution) PCSrc EX/MEM MEM/WB ID/EX WB WB WB RegWrite MemToReg CONTROL M M Branch MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ADD Branch ADD Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  7. 1 MUX 0 Stage 5: Write Back PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ADD Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY ADDRESS READ DATA RESULT MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  8. ADD PC Following a Load Instruction – Clock Cycle 1 LW before<1> before<2> before<3> before<4> PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  9. Following a Load Instruction – Clock Cycle 2 after<1> LW before<1> before<2> before<3> PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ADD Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  10. ADD 0 MUX 1 Following a Load Instruction – Clock Cycle 3 after<2> after<1> LW before<1> before<2> PCSrc MEM/WB EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc ADD Branch RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] RegDst I[20-16] ALUOp I[15-11]

  11. Following a Load Instruction – Clock Cycle 4 after<3> after<2> after<1> LW before<1> PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ADD Branch ADD Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  12. 1 MUX 0 Following a Load Instruction – Clock Cycle 5 LW after<4> after<3> after<2> after<1> PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ADD Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY ADDRESS READ DATA RESULT MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  13. WB WB M M ADD EX ADD ZERO ALU RESULT PC INSTRUCTION MEMORY ADDRESS INSTRUCTION 1 MUX 0 0 MUX 1 Key Concept 1 – Long Registers to Preserve Each Step’s Results PCSrc EX/MEM MEM/WB ID/EX WB 0 RegWrite MemToReg MUX CONTROL Branch 1 MemRead MemWrite RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS READ DATA 1 READ REGISTER 1 / READ DATA 2 READ REGISTER 2 0 DATA MEMORY ADDRESS READ DATA MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[15-0] RegDst I[20-16] ALUOp I[15-11]

  14. WB WB M M ADD EX ADD ZERO ALU RESULT PC INSTRUCTION MEMORY ADDRESS INSTRUCTION 1 MUX 0 0 MUX 1 Key Concept 2 – Set Control Signals Once, Use Long Registers to Remember Them from Step to Step PCSrc EX/MEM MEM/WB ID/EX WB 0 RegWrite MemToReg MUX CONTROL Branch 1 MemRead MemWrite RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS READ DATA 1 READ REGISTER 1 / READ DATA 2 READ REGISTER 2 0 DATA MEMORY ADDRESS READ DATA MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[15-0] RegDst I[20-16] ALUOp I[15-11]

  15. WB WB M M ADD EX ADD ZERO ALU RESULT PC INSTRUCTION MEMORY ADDRESS INSTRUCTION 1 MUX 0 0 MUX 1 Key Concept 3 – Even Remember The Things You Don’t Need Right Away PCSrc EX/MEM MEM/WB ID/EX WB 0 RegWrite MemToReg MUX CONTROL Branch 1 MemRead MemWrite RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS READ DATA 1 READ REGISTER 1 / READ DATA 2 READ REGISTER 2 0 DATA MEMORY ADDRESS READ DATA MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] ALUOp I[15-11]

  16. Following a Set of Instructions LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; this branch will not be taken OR ____,____,____ ADD ____,____,____

  17. LW before<1> before<2> before<3> before<4> ADD PC Following a Set of Instructions – Clock Cycle 1 PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  18. SUB LW before<1> before<2> before<3> ADD PC Following a Set of Instructions – Clock Cycle 2 PCSrc ID/EX EX/MEM MEM/WB WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

  19. BEQ SUB LW before<1> before<2> ADD ADD PC 0 MUX 1 Following a Set of Instructions – Clock Cycle 3 PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] RegDst I[20-16] ALUOp I[15-11]

  20. OR BEQ SUB LW before<1> ADD ADD PC 0 MUX 1 Following a Set of Instructions – Clock Cycle 4 PCSrc EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] ALUOp I[15-11]

  21. ADD OR BEQ SUB LW ADD ADD PC 1 MUX 0 Following a Set of Instructions – Clock Cycle 5 PCSrc EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY ADDRESS READ DATA RESULT MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] 0 ALUOp MUX I[15-11] 1

  22. after<1> ADD OR BEQ SUB ADD ADD PC 1 MUX 0 0 MUX 1 Following a Set of Instructions – Clock Cycle 6 PCSrc EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY ADDRESS READ DATA RESULT MUX WRITE REGISTER 1 WRITE DATA WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] ALUOp I[15-11]

  23. after<2> after<1> ADD OR BEQ ADD ADD PC 0 MUX 1 Following a Set of Instructions – Clock Cycle 7 EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] ALUOp I[15-11]

  24. after<3> after<2> after<1> ADD OR ADD ADD PC 1 MUX 0 Following a Set of Instructions – Clock Cycle 8 EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] 0 ALUOp MUX I[15-11] 1

  25. after<4> after<3> after<2> after<1> ADD ADD ADD PC 1 MUX 0 Following a Set of Instructions – Clock Cycle 9 EX/MEM ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ALUSrc Branch Zero RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[5-0] I[15-0] RegDst I[20-16] 0 ALUOp MUX I[15-11] 1

  26. PCSrc EX/MEM MEM/WB ID/EX WB WB WB 0 RegWrite MemToReg MUX CONTROL M M Branch 1 MemRead MemWrite EX RegDst ALUOp 4 ALUSrc IF/ID ADD Branch ADD RegWrite << 2 MemRead MemWrite MemToReg REGISTERS INSTRUCTION MEMORY READ DATA 1 READ REGISTER 1 / PC ADDRESS INSTRUCTION ZERO READ DATA 2 READ REGISTER 2 0 ALU DATA MEMORY 1 ADDRESS READ DATA RESULT MUX WRITE REGISTER MUX 1 WRITE DATA 0 WRITE DATA ALU CONTROL Sign Extend I[15-0] I[20-16] 0 MUX I[15-11] 1

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