Hardware / Software Codesign Term Project : (1)AMBA BUS (2)Integration ARM and RTOS

1. Hardware / Software Codesign Term Project : (1)AMBA BUS (2)Integration ARM and RTOS D90522024 劉志鵬 F91522803 鍾書耘

2. Agenda • Why Need HW/SW Co-design? • What is our first step? • AMBA BUS • Conclusion 1 • ARM ADS and RTOS Integration • Conclusion 2

3. Why Need HW/SW Co-design? • IC design has ushered in a new era – SoC • System on a Chip

4. Why Need HW/SW Co-design? • What is SoC?

5. Why Need HW/SW Co-design? • What is our first step? • Processor? • Memory? • Operating System? • Peripheral Interface? • CAD Tools? • What else?

6. What is our first step? • Core IP (Processor) • PC && Workstation • Intel Pentium • Ultra SPARC • MIPS • Micro-Controller • 8051 • DSP • TI, • SoC • ARM • Power PC • Configurable Tensilica Processor • SOPC • Altera – Nios • Xillinx – Micro-Blaze • Is there any opportunity for us in this area?

7. What is our first step? • Memories Design is our chance? • Process? • Operating System is another opportunity? • PC & Workstation • Windows • Unix – Solaris, HP-Unix • Linux • RTOS • eCos • Micrium uC/OSII • Shugyo Design  KROS • Accelerated Technology  Nucleus Plus • VxWork • Embedded System • Windows CE • uCLinux

8. What is our first step? • Peripheral IP Design is one way for us? • PrimeCell – ARM • Synopsys – • FPGA Vendor -- • Open Core Web Site –www.opencores.org • . . . • EDA CAD Tool? • Cadence • Synopsys • Mentor • 思源科技

10. What is our first step? • Can We Find Our Way in SoC or HW/SW Co-design Era? • Master in applications • ASIC • SW • Time to Market is another important thing • Use Well-Design IP • Embedded Linux, RTOS • What else? • Integration • System is the keyword of SoC • How to transition from on-board design to on-chip design? • AMBA Bus (One Important Issue) • Advanced Microcontroller Bus Architecture

11. AMBA BUS

12. AMBA BUS

13. AMBA BUS • AMBA Buses • Advanced System Bus (ASB) • Advanced High-Performance Bus (AHB) • Processors • On-Chip Memory • Off-Chip External Memory with low power peripheral macrocell • Bridge : to APB • High Speed ASIC –Your Design • … • Advanced Peripheral Bus (APB) • Peripheral Interface • UART • Timer • Low Speed ASIC –Your Design • …

14. AMBA BUS • Advanced High-Performance Bus : AHB

15. AMBA BUS • Advanced High-Performance Bus : AHB

16. AMBA BUS  AHB • Advanced High-Performance Bus : AHB • AHB master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time.(max. 16) • AHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer. • AHB arbiter ensures that only one bus master at a time is allowed to initiate data transfers. • AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.

17. AMBA BUS  AHB

18. AMBA BUS  AHB

19. AMBA BUS  AHB • Basic Transfer of AHB

20. AMBA BUS  AHB • Transfer Types of AHB

21. AMBA BUS  AHB • Burst Operation of AHB

22. AMBA BUS  AHB • Incrementing bursts access sequential locations and the address of each transfer in the burst is just an increment of the previous address. • An incrementing burst can be of any length, but the upper limit is set by the fact that the address must not cross a 1kB boundary • For wrapping bursts, if the start address of the transfer is not aligned to the total number of bytes in the burst (size x beats) then the address of the transfers in the burst will wrap when the boundary is reached. For example, a four-beat wrapping burst of word (4-byte) accesses will wrap at 16-byte boundaries. Therefore, if the start address of the transfer is 0x34, then it consists of four transfers to addresses 0x34, 0x38, 0x3C and 0x30.

23. AMBA BUS  AHB • There are certain circumstances when a burst will not be allowed to complete and therefore it is important that any slave design which makes use of the burst information can take the correct course of action if the burst is terminated early. The slave can determine when a burst has terminated early by monitoring the HTRANS signals and ensuring that after the start of the burst every transfer is labelled as SEQUENTIAL or BUSY. If a NONSEQUENTIAL or IDLE transfer occurs then this indicates that a new burst has started and therefore the previous one must have been terminated.

24. AMBA BUS  AHB

25. AMBA BUS  AHB

26. AMBA BUS  AHB • HSIZE[2:0] of AHB

27. AMBA BUS  AHB • The protection control signals, HPROT[3:0] of AHB

28. AMBA BUS  AHB • AHB Bus Slave

29. AMBA BUS  AHB • AHB Bus Master

30. AMBA BUS  AHB • AHB Arbiter

31. AMBA BUS  AHB • AHB Decoder

32. AMBA BUS  APB • Advanced Peripheral Bus : APB • The AMBA APB should be used to interface to any peripherals which are lowbandwidth and do not require the high performance of a pipelined bus interface.

33. AMBA BUS  APB

34. AMBA BUS  APB • IDLE • The default state for the peripheral bus. • SETUP • When a transfer is required the bus moves into the SETUP state, where the appropriate select signal, PSELx, is asserted. The bus only remains in the SETUP state for one clock cycle and will always move to the ENABLEstate on the next rising edge of the clock. • ENABLE • In the ENABLE state the enable signal, PENABLEis asserted. The address, write and select signals all remain stable during the transition from the SETUP to ENABLE state. The ENABLE state also only lasts fora single clock cycle and after this state the bus will return to the IDLE state if no further transfers are required. Alternatively, if another transfer is to follow then the bus will move directly to the SETUP state. It is acceptable for the address, write and select signals to glitch during a transition from the ENABLE to SETUP states.

35. AMBA BUS  APB • Write Transfer of APB

36. AMBA BUS  APB • Read Transfer of APB

37. AMBA BUS  APB • APB Bridge

38. AMBA BUS  APB • APB Slave

39. Conclusion • What do you want in SoC era?

40. （2）Integrate uC/OS-II into ARM Development Suite （ADS） D90522024 劉志鵬 F91522803 鍾書耘

41. Introduction to ADS • Experiment 1 • Analysis of ARM and Thumb instruction • Experiment 2 • Integrate UC/OSII into ADS

42. ARM Development Suite （ADS） • Project management • Configuring the settings of build targets for project

43. The Structure of ARM Tools

44. Main components of ADS • ANSI C compilers- armcc, tcc • ISO/Embedded C++ compilers – armcpp, tcpp • ARM/Thumb assembler- armasm • Linker – armlink • Project management tool –CodeWarrior • Instruction set simulator –ARMulator • Debuggers –AXD, ADW, ADU and armsd • Format converter – fromelf • Libarian – armar • ARM profiler – armprof

45. CodeWarrier • Provides a simple, versatile graphical user interface for managing your software development projects • Develop C,C++, and ARM assembly language code • Targeted at ARM and Thumb processors

46. Create New Project Project File View Target Setting Editor Window

47. AXD • Various views allow you to examine and control the processes you are debugging

49. ARMulator • A suite of programs that models the behavior of various ARM processor cores and system architecture in software on a host system • Can be operates at various levels of accuracy • Instruction accurate • Cycle accurate • Timing accurate • Benchmarking before hardware is available

50. Introduction to ADS • Experiment 1 • Analysis of ARM and Thumb instruction • Experiment 2 • Integrate UC/OSII into ADS