Problem sets/ EE382 Project: Starting with Verilog

1. Problem sets/ EE382 Project:Starting with Verilog 2012 - EE382 - 16905 Veynu Narasiman Carlos Villavieja

2. Course website • http://www.ece.utexas.edu/~patt/12s.382N/

3. Problem Sets • The course has two different parts: • Small set of problems - individual • ALU design • ALU implementation • Datapath design for several x86 instructions • Control logic design • The project - groups of 3 people • Build a 1 wide-issue in-order x86 processor running a limited set of instructions • A set of instructions will be published in the course website

4. Tools location Machines in ECE: http://www.ece.utexas.edu/it/remote_linux.cfm Forget about sunservers Tools Path: /usr/local/packages/synopsys_2011/vcs-mx/bin/vcs

5. Some documentation • /usr/local/packages/synopsys_2011/vcs-mx/doc/help_vcs.txt • /usr/local/packages/synopsys_2011/vcs-mx/doc/ • /usr/local/packages/synopsys_2011/vcs-mx/doc/UserGuide/ • /usr/local/packages/synopsys_2011/vcs-mx/doc/UserGuide/pdf/ • /usr/local/packages/synopsys_2011/vcs-mx/doc/UserGuide/pdf/mvsim_native.pdf

6. Let's start Setting up the environment: Load the compiler modules • module load synopsys/vcs • module initadd synopsys/vcs

7. High level diagram Latch D Q Wen Qbar Source code at : http://www.ece.utexas.edu/~patt/12s.382N/tools/vcs_manual.html

8. D D D S Wen Q R Qbar Wen D Wen S R Q Qbar 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 0 1 0 1 1 X 0 X 1 X 1 X 0

9. Compiling and Running • cat master /home/projects/courses/spring-12/ee382n-16905/lib/time -v /home/projects/courses/spring-12/ee382n-16905/lib/lib1 d-latch.v • vcs –debug_all -f master • You will have a binary file ./simv Run and generate the timing info • ./simv -v: only modules instantiated are compiled

10. Visualization tool - dve • ssh –x username@mario.ece.utexas.edu • Or connecting through VNC – see instructions on the course webpage • dve • File – Open Database - .dump.vpd file

11. Starting dve

12. Waveform result

13. Debug – step by step