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High Speed Wired Data Collection

High Speed Wired Data Collection. Honeywell Bob Dearth Michael Retzler Brad Lucht ISU Prof. Zhengdao Wang Zachary Coffin, Cpr E Radell Young, E E Mazdee Masud , E E. Problem and Need Statements.

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High Speed Wired Data Collection

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  1. High Speed Wired Data Collection Honeywell Bob Dearth Michael Retzler Brad Lucht ISU Prof. Zhengdao Wang Zachary Coffin, Cpr E Radell Young, E E MazdeeMasud, E E

  2. Problem and Need Statements • Honeywell’s Kansas City Plant needs a method to collect experimental data very quickly over a distance of 300 feet. • All previous designs are now too slow and error-prone to collect useful data.

  3. Conceptual Description • A remote device will acquire, encode, and transmit digital data samples. • A local device will receive the communication, decode, and send data via USB to simple acquisition software on a Windows PC.

  4. System Block Diagram

  5. Operating Environment • The tests shall be run in a controlled facility. • Remote device will be destroyed at the conclusion of every test, however local receiver may be reused.

  6. Functional requirements • Sample two analog voltage signals (5 Vpk) • Sample two analog current signals (20 mApk) • Sample resolution: 8-bit per channel (minimum) • Sample frequency: 2 million samples/second (minimum) • Wired distance of 300 ft • Latency as low as 0.5 μs, (5 μs maximum) • Volume no greater than 3 x 3 x ½ inches

  7. Market/literature survey • Pre-existing devices and protocols have limitations which inhibit their use in this application. The combination of 300 feet of distance, 64Mbit/sec minimum transfer rate, and latency on the order of 0.5 microseconds makes this project challenging.

  8. Deliverables • Prototypes of the transmitting and receiving devices shall be constructed and brought to Kansas City for verification.

  9. Project Plan – Work Breakdown

  10. Project Plan – Resource Requirements

  11. Project Plan – Risks • Transmission scheme may not work over the 300 ft distance • Modular design will allow for interchangeable modulation/demodulation schemes. • Bit error rate may be too high to collect usable data. • Header and footer to each sample may be modified, cable may be more sophisticated. • Large time commitment to research leaves little time for design and implementation.

  12. Cost Estimate

  13. Project Plan – Schedule

  14. System Design – Functional Decomposition • Analog to Digital Conversion • Error Detection/Correction • Modulation • Transmission and Synchronization • Demodulation • Data to Windows XP

  15. System Design • Current signals converted to voltage signals with shunt resistances • AtoD – Texas Instruments TLC5510 • Parity – Texas Instruments HC280 • Modulation – Serialization to Differential Voltage through a series of MUX translations • Analog Devices ADG732 32to1 MUX (data channels) • Analog Devices ADG1608 8to1 MUX (data vs parity) • Analog Devices AD8180 2to1 MUX (x2 for LVDS) • Transmission and Synchronization • Demodulation • Data to Windows XP

  16. Detailed Design – System I/O Specification • Remote inputs include two voltage signals at 5Vpk and two current signals at 20mApk. • Local inputs include a signal to start recording data, a signal to stop recording data, and a path and file name to save the sample data. • Local output consists of a single .CSV file per experimental trial.

  17. Detailed Design – Module I/O Specification • Remote device shall output a modulated signal representing experimental data and timing information. • This signal shall be received by the local device, which shall demodulate and push data to a USB transceiver. • A USB transceiver shall then transmit data to a Windows XP PC with proper drivers and data acquisition program.

  18. Detailed Design – User Interface Specification • The remote device shall continuously transmit sample data until device destruction or termination of power supply. • The local device shall continuously collect data until remote termination. • A command-line Windows XP program will read data from the local device and save output in .CSV format.

  19. Detailed Design – Hardware Specification • ADC:Texas Instruments TLC5510 • Parity error detection encoding and decoding: Texas Instruments HC280 • Modulation – multiplexers from Analog Devices: ADG732, ADG1608, and AD8180. • Cable – one of: Cat-3 UTP, Cat-5e UTP, Cat-6 UTP, RG-59 coaxial, RG-6 coaxial. Clock signal shall be generated by Texas Instruments CDCE913 • USB Transceiver: SMSC USB3317

  20. Detailed Design – Software Specification • Driver for USB device written in C using Microsoft Driver Kit 7.1.0 • Command-line data acquisition program to read data from USB device and export to .CSV

  21. Testing Plan – Unit Testing • In this phase we will be making sure that all components (e.g. sensors, ADCs, transceivers, etc) are behaving according to individual specifications. • This will be accomplished by providing various input voltages while monitoring output(s).

  22. Testing Plan – Integration Testing • In this phase we will put each individual component together and see if they can interface with one another without problems. • Hardware from a single manufacturer may interface more smoothly than from multiple sources.

  23. Testing Plan – System Testing • In this phase we will test the entire system simulating the crash at the end by either disconnecting the cable or shorting all transmitting conductors together.

  24. Testing Plan – Sample Test Cases • 300 foot spool of cable • Prototype transmitting and receiving boards at either end • Input voltages and currents are stepped • Output verified on Windows PC

  25. Evaluation Plan – Simulation, Modeling, PrototypingPerformance Metrics • Success will be determined initially at testing if the prototype system meets the speed and accuracy requirements. Moreover, at the Demonstration the device must work and the production cost of future modules must be within the budget of $100ea.

  26. Evaluation Plan – Simulation, Modeling, PrototypingValidation Means • There will be a demonstration on site in Kansas City Honeywell Plan to exhibit the functionality of our system. The collected/transferred data will be displayed via spreadsheet program on PC in .CSV format for verification.

  27. Conclusion – Current Status • Different modulation schemes were considered and, consequently we are behind schedule. • Parts will be ordered this summer and assembled for the beginning of Fall semester.

  28. Conclusion – Task Responsibility / Contributions

  29. Conclusion – Plan for Next Semester • Modules will be assembled and tested throughout the semester. • New sets of modulation chips may be necessary to implement an alternative transmission scheme.

  30. Questions / Answers

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