FINESSE MODULE signals and functionality description

1. FINESSE MODULEsignals and functionality description [One Event split (1-12 & 13-24 channels) -> Two FIFOS] FINESSE HARDWARE status Zbigniew Natkaniec, Wacek Ostrowicz Kraków 23.05.2007

2. Signals between FADC and FINESSE (1) - timing -> DCLK+/- -> DAEN+/- -> XD+/-[31:0] MAIN HEADER FOOTER DATA n DATA 2 DATA 1 INPUT HEADER MAIN HEADER FOOTER One Event -> XD+/-[31] -> HEADER+/- -> HALF_EV+/- CHANNELS 13-24 CHANNELS 1-12 -> TRAILER+/- <- BSYFD+/- Space for 8 words more in FINESSE For confirmation by FADC side

3. Signals between FADC and FINESSE (2) <- TYP[3:0] <- TAG[7:0] Direct from the COPPER (drivers) <- TRG <- SCK -> ADCBSY Causes the same action as FFUL and NWFF – for discussion <- ADCRST Inverted IRSTB signal – for discussion -> ADC_ERR Not implemented – for discussion For confirmation by FADC side

4. DATA from FADC to FIFOs - Data flow FADC Trailer Channels 16 - 09 Channels 08 - 01 FADC Main Header COPPER Channels 08 - 01 FADC Main Header Finesse Trailer U Channels 08 - 01 FADC Main Header Finesse Header FIFO U Channels 16 - 09 FADC Main Header Finesse Trailer D Channels 16 - 09 FADC Main Header Finesse Header FIFO D For confirmation by COPPER side

5. DATA from FADC to FIFOs - headers and trailers Finesse Header F F A A 0 0 0 0 Two words Finesse event number Error Field Type of Data + Time between Clock and Trigger + ADC Module Number + Event Number from Copper System FADC Main Header One word Finesse Trailer U or D One word F F 5 5 Checksum U or D For confirmation by COPPER side

6. DATA from FADC to FIFOs - Errors checking FADC FINESSE COPPER FADC checksum comparator Checksum Error Finesse checksum Copper Event Number (Event Tag) Copper Event Number comparator Event Number Error Copper Event Number from FADC Finesse Event Number Trigger counter

7. DATA from FADC to FIFOs - Errors Field Finesse Header F F A A 0 0 0 0 Finesse event number A = B = C 0 0 0 0 Checksums equal A = B != C 0 0 1 1 Checksums not equal A = C != B 0 1 0 B = C != A 1 0 0 A != B != C 1 1 1 where A => Copper Event Number B => Copper Event Number from FADC C => Finesse Event Number For confirmation by COPPER side

8. Signals between COPPER and FINESSE (1) - timing <- FWCLK <- FWENB <- FF[31:0] FINESSE TRAILER DATA n FINESSE TRAILER DATA 2 DATA 1 FADC INPUT HEADER FADC MAIN HEADER FINESSE HEADER FINESSE HEADER Continuous data Half of Event CHANNELS 1-12 or 13-24 min 2T of FWCLK min 2T of FWCLK <- FRSTB not used For confirmation by COPPER side

9. Signals between COPPER and FINESSE (2) - timing normal work - BSYB as acknowledge -> SCK -> TRG <- BSYB 2T of SCK width -> FFUL or -> NWFF or -> ADCBSY FIFOs on COPPER or FADC full - BSYB stopping trigger -> SCK -> TRG <- BSYB -> FFUL or -> NWFF or -> ADCBSY For confirmation by COPPER side

10. Signals between COPPER and FINESSE (3) -> TYP[3:0] -> TAG[7:0] Direct to the FADC (drivers) -> TRG according to T. Higuchi – FINESSE Developer’s Guide -> SCK -> IRSTB Set all FIFOs, counters, state machines and FFs on FINESSE in initial state (all data lost) -> LD[7:0] -> LA[6:0] -> LRW -> CSB For confirmation by COPPER side

11. The design is based on: • Vienna presentation 08.11.2006 • T. Higuchi – FINESSE Developer’s Guide. Belle Note #791 • FINESSE-timing-chart.ppt

12. Hardware status 1. Two Boards in Krakow 2. The module is operational 3. Basic tests done with success – test events written to COPPER FIFOs. • 4. Found two problems: • No possibility to reset logic in two out FIFOs after ‘RESET’ command send to register – solution: add wires • - Only one CE track from COPPER connectors – solution: add wire