Final Exam Project

1. Final Exam Project 4 bit Full Adder Layout and Analysis using Lasi and WinSpice

2. Assignment Objectives • Do a hierarchal layout of a half adder, full adder and 4 bit adder using LASI, then simulate the circuit using SPICE to make sure that the design will work.

3. Overview • Hierarchal Layout design is done using Lasi. • N3X2, P3X2, NAND, XOR, Half-Adder, Full-Adder and 4 bit Full Adder layouts are made in hierarchal sfashion using bottom up approach. • Each Cell is analyzed by using Winspice3 .CIR file created by Lasi.

4. P3X2 (Rank 1)Cell- Standard cell from Lasi Library

5. N3X2 (Rank 2) Cell -Standard cell from Lasi Library

6. INVERTER (Cont’d) • Inverter cell has Rank 2. • Inverter cell is made using P3X2 and N3X2 cell. • It is used to provide A’ and B’ for XOR input and NAND input to make OR gate.Also it is used at output of a NAND to make AND.

7. INVERTER

8. NAND (Cont’d) • NAND cell has rank 2. • It is used to make AND gate and OR gate.

9. NAND

10. XOR (Cont’d) • XOR cell has Rank 2. • It is is made to provide sum of Half Adder. • It is little different than regular XOR because it requires four inputs A, A’, B, and B’. • By designing in with four inputs we simplify design and reduced transistors.

11. XOR

12. Half-Adder (Cont’d) • Half-Adder has rank 3. • It is designed using INVERTER, NAND and XOR gate. • Sum = AB’ + B’A. • Carry = AB.

13. Half-Adder

14. Full-Adder (Cont’d) • It has rank 4. • Full adder is made using two HALF-ADDER , 2 Inverter and a NAND gate. • S1 = HA(A,B) • Sum = HA(S1,Carry In) • Carry = OR(Carry 1,Carry 2)

15. Full-Adder

16. 4 Bit Full Adder (Cont’d) • It has rank 5. • It is made using four 1 bit Full-Adder. • First Full-Adder has Carry in 0. • 4th Carry out is Final Carry out of 4 bit Full-Adder.

17. 4 Bit Full Adder

18. SPICE SIMULATION • Each cell is compiled using LasiCkt. • Generate .CIR files used in WinSpice3 for simulation of circuit. • Every analyzed signal is offset by 6V to see each signal properly.

19. INVERTER Simulation (Cont’d) • Next slide shows screen capture of Inverter simulation. • A_ is output of signal input signal A.

20. INVERTER Simulation

21. NAND Simulation (Cont’d) • Next slide show simulation of NAND gate. • AB_ is output of NAND gate. • 11,10,01,00 signals analyzed.

22. NAND Simulation

23. XOR Simulation (Cont’d) • Next slide show simulation of XOR gate. • AXORB is output of XOR gate. • 11,10,01,00 signals analyzed. • It is Sum of Half-Adder.

24. XOR Simulation

25. Half-Adder Simulation (Cont’d) • Next slide show simulation of Half-Adder gate. • S is Sum and C is carry. • 11,10,01,00 signals analyzed.

26. Half-Adder Simulation

27. Full-Adder Simulation(Cont’d) • Next slide show simulation of full adder. • All the combination from 000 to 111 is used as Cin, B and A inputs.

28. Full-Adder Simulation

29. 4 Bit Full Adder Simulation (Cont’d) • Next four slides shows simulation of 4 bit Full Adder. • Individual plot used each inputs for proper demonstration. • VN4 is Carry out 1. • VN5 is Carry out 2. • VN6 is Carry out 3.

30. 4 Bit Full Adder Simulation- A0+B0 (Cont’d)

31. 4 Bit Full Adder Simulation- A1+B1 (Cont’d)

32. 4 Bit Full Adder Simulation- A2+B2 (Cont’d)

33. 4 Bit Full Adder Simulation- A3+B3 (Cont’d)

34. Related Documents • Included floppy contains two directories LASI and CIR. • LASI Directory Contains all the Layout files and other required files to open layouts in LASI . • To open LASI Layout files create shortcut of LASI executable file, and change the “Start in” option through properties to A:\ LASI \. • Circuit simulation .CIR files are located in CIR directories.