Low Noise Power Supply Circuit Design: Enhancing Di/dt Performance

1. Junfeng Zhou Wim Dehaene AID–EMC: Low Emission Digital Circuit Design Update of the “Digital EMC project” September 2nd, 2005

2. Outline of presentation • Outline: • Low noise logic families • Comparison • Conclusion • Low noise Power Supply circuit • Principles • Switching mode • Continuous mode • Conclusion • Questions on the test chip

3. Problem with CSL and C-CBL C-CBL: • Bad process variation behaviour • sizing for optimal current balance is really difficult CSL: • rather slow • power hungry • low logic swing Fig.2 C-CBL inverter Fig.1 CSL inverter

4. Solution- Enhanced current steering logic • Still current source basing • Increase in logic level, hence increase the robustness • Reduced output capacitance, hence the speed is increased Fig.3 E-CSL inverter

5. Comparison of CSL, C-CBL, ECSL and SCMOS Fig.4 power vs. frequency Fig.5 di/dt vs. frequency

6. di/dt performance vs. process variation Fig.6 di/dt vs. process corner

7. Comparison of 16-bit RCA Fig.7 power vs. frequency Fig.8 di/dt vs. frequency

8. Conclusion of low noise logic families • Current source ensures the major di/dt reduction, • Process variation sensitivity also becomes better due to the dominance of current source, • E-CSL gives comparable di/dt performance with CSL, • E-CSL is Faster and Less power consumption than CSL due to the lower area and lower capacitance. Winner is E-CSL

9. Problems and proposal However 2 problems still remain: • Static power consumption • New logic family standard cell must be designed and characterised ?? Is there any global approach ??

10. Principles of low noise power supply Current source ensures the major di/dt reduction Do not give more current the circuit needs, i.e. minimize the static current 3. Slow varying is key to EMC success Fig.9 Diagram of Low noise power supply

11. Option 1- Switching mode power delivery Determine the switching speed, hence determine the di/dt Energy reservoir when slow Switching Fig.10 Switching mode power delivery system

12. Functionality verification of option 1 9v 8v 7v 12v supply current Out_0 Out_1 Out_2 VDD_input 12v supply current di/dt Fig.11 Function simulation of the switching mode power supply circuits

13. Comparison with standard CMOS 105 times= 40dB 12v supply current 3.3v supply current w/o SW 12v supply current di/dt , P-P= 5.0e7 A/s 3.3v supply current di/dt w/o SW, P-P= 1.51e11 A/s Fig.12 di/dt and FFT comparison with standard CMOS

14. Option 2- Continuous mode power delivery Still under investigation continuous time OTA feedback loop stable Determine the switching speed, Hence determine the di/dt Energy reservoir when slow Switching Fig.13 Continuous time power delivery system

15. Functionality Simulation of option 2 9v 12v supply current VDD_input 2nd order under damped behaviour , still under study continuous time OTA feedback loop stable Vcontrol 12v supply current di/dt Fig.14 Functionality simulation of continuous time power delivery system

16. Comparison with standard CMOS 12v supply current 162 times= 44dB 3.3v supply current w/o CT 12v supply current di/dt, P-P= 1.0e7 A/s 3.3v supply current di/dt w/o CT, P-P=1.51e11 A/s Fig.15 di/dt and FFT comparison with standard CMOS

17. Conclusion of low noise power supply • Both approaches give comparable simulation results, • Both approaches have potential stability problem as in any feedback loop, • Switching mode : easy design, • Continuous mode : more difficult to design but potentially has better di/dt suppression.

18. What is the next step • Figure out current behaviour of a typical AMIS digital block • Decide between switching mode and continuous mode: • more simulation required • theory of stability to be analyzed further • Test chip in I3T80

19. Proposal Test chip Proposal: 1. Can we get a series regulator ? (for example, 12V  3.3V) and/ or 2. Test structure for low noise logic families

20. Questions Thank you for your attention