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Junfeng Zhou Wim Dehaene

AID–EMC: Low Emission Digital Circuit Design. Status of the “Digital EMC project”. Junfeng Zhou Wim Dehaene. Logic styles under investigation. Logic style. Standard CMOS logic Pseudo NMOS logic CSL (CMOS Current Steering Logic)

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Junfeng Zhou Wim Dehaene

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  1. AID–EMC: Low Emission Digital Circuit Design Status of the “Digital EMC project” Junfeng Zhou Wim Dehaene

  2. Logic styles under investigation Logic style • Standard CMOS logic • Pseudo NMOS logic • CSL (CMOS Current Steering Logic) • MCML (MOS Current Mode Logic--differential version of CSL)

  3. Why CSL ? Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Current Steering Logic

  4. CSL – Static Characteristic Vdd=2.5v I=20uA Cload=20fF Design Parameter: R=

  5. CSL – Noise Margin 300mV R >4 Vdd=2.5v I=20uA Cload=20fF

  6. CSL – Dynamic Characteristic Vdd=2.5v I=20uA Cload=20fF

  7. The Effect of Decoupling Capacitance Vdd=3.3v I=10uA R=6 Cload=20fF 1p Cd 10p,100p,1n,10n di/dt There is a Trade off !

  8. Comparison of 16-bit RCA, CSL vs. SCMOS Note: VDD=1.5v The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. • Solution: • power consumption management • power down , sleep transistors, • switching activity improvement • …

  9. Spectrum Analysis of di/dt Power Spectral Analysis of the CMOS 16-bit RCA 150 140 30db decrease 130 120 110 Power 100 90 80 70 5 6 7 8 9 10 10 10 10 10 10 10 Frequency (Hz)

  10. Variants of CMOS inverter Variant 1 Variant 2

  11. The effect of decoupling capacitance • Time domain 100pF 10pF 1nF 1pF 100fF 10fF

  12. The effect of decoupling capacitance Bit rate=100MHz • Frequency domain

  13. CSL D-type Flip-Flop master slave

  14. Comparison of D-FF Spectrum, CSL vs. SCMOS Clock=50MHz 38dB reduction

  15. Intentional clock skew • Principle • Circuit under Simulation

  16. The effect of clock skew on the reduction of di/dt 120ps skew No skew • Time domain

  17. The effect of clock skew on the reduction of di/dt • Frequency domain

  18. Spread Spectrum Clocking ---SSC 1. Frequency modulating(FM) the clock signal with a unique modulating waveform. 2. The total power of the switching noise remains the same. Figure 1. Frequency domain representation at a harmonic of a clock signal with and without SSC Figure 2. Time domain representation of the modulated clock signal Hardin, K.B. Fessler, J.T. Bush, D.R., ” Spread spectrum clock generation for the reduction of radiated emissions”, IEEE International Symposium on Electromagnetic Compatibility, 1994, pp 227-231

  19. Digital Pseudo Random Modulation-PRM Figure 3 Circuit implementation of PRM Figure 4 Timing diagram of PRM

  20. Test circuit Fnominal = 40MHz Fmodulation = 1GHz N=3,M=8 Figure 5 Test circuit under simulation

  21. Comparison of Spectrum Regular Clock Zoom in Spread Spectrum Clock 12dB reduction Promising ... promising Figure 6 Spectrum from 300MHz to 800MHz

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