Virtual Memory

1. Virtual Memory Rabi Mahapatra & Hank Walker Adapted from lecture notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley

2. { Thus far { Next: Virtual Memory View of Memory Hierarchies Regs Upper Level Instr. Operands Faster Cache Blocks L2 Cache Blocks Memory Pages Disk Files Larger Tape Lower Level

3. Memory Hierarchy: Some Facts Upper Level Capacity Access Time Cost Staging Xfer Unit faster CPU Registers 100s Bytes <10s ns Registers prog./compiler 1-8 bytes Instr. Operands Cache K Bytes 10-100 ns $.01-.001/bit Cache cache cntl 8-128 bytes Blocks Main Memory M Bytes 100ns-1us $.01-.001 Memory OS 512-4K bytes Pages Disk G Bytes ms 10 - 10 cents Disk -4 -3 user/operator Mbytes Files Larger Tape infinite sec-min 10 Tape Lower Level -6

4. Virtual Memory: Motivation • If Principle of Locality allows caches to offer (usually) speed of cache memory with size of DRAM memory,then recursively why not use at next level to give speed of DRAM memory, size of Disk memory? • Treat Memory as “cache” for Disk !!!

5. Translation: • Program can be given consistent view of memory, even though physical memory is scrambled • Makes multithreading reasonable (now used a lot!) • Only the most important part of program (“Working Set”) must be in physical memory. • Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later. • Protection: • Different threads (or processes) protected from each other. • Different pages can be given special behavior • (Read Only, Invisible to user programs, etc). • Kernel data protected from User programs • Very important for protection from malicious programs=> Far more “viruses” under Microsoft Windows • Sharing: • Can map same physical page to multiple users(“Shared memory”) Advantages of Virtual Memory

6. Virtual Address: page no. offset Page Table ... Page Table Base Reg V A.R. P. P. A. + index into page table Access Rights Physical Page Address Val -id Physical Memory Address . ... Virtual Memory Mapping (actually, concatenation) Page Table located in physical memory

7. Issues in VM Design What is the size of information blocks that are transferred from secondary to main storage (M)?  page size(Contrast with physical block size on disk, I.e. sector size) Which region of M is to hold the new block placement policy How do we find a page when we look for it?  block identification Block of information brought into M, and M is full, then some region of M must be released to make room for the new block  replacement policy What do we do on a write?  write policy Missing item fetched from secondary memory only on the occurrence of a fault demand load policy disk mem cache reg pages frame

8. Virtual to Physical Address Translation Program operates in its virtual address space Physical memory (incl. caches) HW mapping virtual address (inst. fetch load, store) physical address (inst. fetch load, store) • Each program operates in its own virtual address space; ~only program running • Each is protected from the other • OS can decide where each goes in memory • Hardware (HW) provides virtual -> physical mapping

9. Code Static Heap Mapping Virtual Memory to Physical Memory • Divide into equal sizedchunks (about 4KB) ¥ Stack • Any chunk of Virtual Memory assigned to any chuck of Physical Memory (“page”) Physical Memory 64 MB 0 0

10. Virtual Address Physical Address page 0 0 1K page 0 1K 0 page 1 1K 1024 1K page 1 Addr Trans MAP 1024 ... ... ... page 2 1K 2048 ... ... ... page 7 1K 7168 page 31 1K Physical Memory 31744 Virtual Memory Paging Organization (eg: 1KB Page) Page is unit of mapping Page also unit of transfer from disk to physical memory

11. Virtual Memory Problem # 1 • Map every address  1 extra memory access for every memory access • Observation: since locality in pages of data, must be locality in virtual addresses of those pages • Why not use a cache of virtual to physical address translations to make translation fast? (small is fast) • For historical reasons, cache is called a Translation Lookaside Buffer, or TLB

12. Virtual Memory Problem # 2 miss PA VA Trans- lation Cache Main Memory Processor hit data • Cache typically operates on physical addresses • Page Table access is another memory access for each program memory access! • Need to fix this!

13. Virtual Memory Problem # 2 • Map every address  1 extra cache (TLB) access for every memory access • Why not just have cache use virtual addresses? • Problem: Different processes use same virtual addresses • Could invalidate cache on context switch, but results in lots of compulsory misses • Prefix addresses with process ID • Other issues with virtual caches…

14. Virtual Memory Problem #2 • Note: Only high order bits of address are translated, low order bits are not translated • Feed low order index bits to cache while also doing translation • Get translated tag and match with cache • TLB is usually smaller and faster, so has translation ready before tag is ready • Why it is called a translation LOOKASIDE buffer

15. Lookaside VPN PI VA Virtual Page # Page Index TLB TLB • Works if page bits >= index+offset size • Example: • 4 KB page => 12 bit page index • 256 lines of 16-byte blocks => 8 index, 4 offset bits • But only 256*16=4 KB cache size! • Solution: Use larger set size • 16-way cache would be 64 KB • Solution: Use larger page size • But causes internal fragmentation – unused part of page Hit = PA Physical Page # Page Index Tag Data Tag Index Offset To CPU

16. Typical TLB Format Virtual Physical Dirty Ref Valid Access Address Address Rights • TLB just a cache on the page table mappings • TLB access time comparable to cache (much less than main memory access time) • Ref: Used to help calculate LRU on replacement • Dirty: since use write back, need to know whether or not to write page to disk when replaced

17. What if not in TLB • Option 1: Hardware checks page table and loads new Page Table Entry into TLB • Option 2: Hardware traps to OS, up to OS to decide what to do • MIPS follows Option 2: Hardware knows nothing about page table format

18. TLB Miss • If the address is not in the TLB, MIPS traps to the operating system • The operating system knows which program caused the TLB fault, page fault, and knows what the virtual address desired was requested valid virtual physical 1 2 9

19. TLB Miss: If data is in Memory • We simply add the entry to the TLB, evicting an old entry from the TLB valid virtual physical 1 7 32 1 2 9

20. What if data is on disk ? • We load the page off the disk into a free block of memory, using a DMA transfer • Meantime we switch to some other process waiting to be run • When the DMA is complete, we get an interrupt and update the process's page table • So when we switch back to the task, the desired data will be in memory

21. What if the memory is full ? • We load the page off the disk into a free block of memory, using a DMA transfer • Meantime we switch to some other process waiting to be run • When the DMA is complete, we get an interrupt and update the process's page table • So when we switch back to the task, the desired data will be in memory

22. Memory Organization with TLB • TLBs usually small, typically 128 - 256 entries • Like any other cache, the TLB can be fully associative, set associative, or direct mapped hit PA miss VA TLB Lookup Cache Main Memory Processor miss hit Trans- lation data

23. Virtual Memory Problem # 3 • Page Table too big! • 4GB Virtual Memory ÷ 4 KB page ~ 1 million Page Table Entries 4 MB just for Page Table for 1 process, 25 processes  100 MB for Page Tables! • Variety of solutions to tradeoff memory size of mapping function for slower when miss TLB • Make TLB large enough, highly associative so rarely miss on address translation

24. Virtual Memory 2nd Level Page Tables ¥ Super Page Table Stack Physical Memory 64 MB ... Code Static Heap 0 0 Two Level Page Tables

25. Summary • Apply Principle of Locality Recursively • Reduce Miss Penalty? add a (L2) cache • Manage memory to disk? Treat as cache • Included protection as bonus, now critical • Use Page Table of mappings vs. tag/data in cache • Virtual memory to Physical Memory Translation too slow? • Add a cache of Virtual to Physical Address Translations, called a TLB

26. Summary • Virtual Memory allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound • Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well • TLB to reduce performance cost of VM • Need more compact representation to reduce memory size cost of simple 1-level page table (especially 32-  64-bit address)