1 / 15

Radiation Effects in FPGAs & SEU Modelling Methodology Ketil Røed Høgskolen i Bergen

Radiation Effects in FPGAs & SEU Modelling Methodology Ketil Røed Høgskolen i Bergen. Topics. Radiation effects in the TPC Front End Electronics Single Event Upset in an FPGA Radiation testing and result Next step: SEU modelling Methodology & Preparation work. 010100 010101 010101

dattilo
Download Presentation

Radiation Effects in FPGAs & SEU Modelling Methodology Ketil Røed Høgskolen i Bergen

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Radiation Effects in FPGAs & SEU Modelling Methodology Ketil Røed Høgskolen i Bergen

  2. Topics • Radiation effects in the TPC Front End Electronics • Single Event Upset in an FPGA • Radiation testing and result • Next step: SEU modelling • Methodology & Preparation work

  3. 010100 010101 010101 101011 111100 FPGA and Single Event Upset • Field Programmable Gate Array (programmable device) • Design stored in SRAM based memory

  4. 010100 010101 010101 101011 111100 FPGA and Single Event Upset • Field Programmable Gate Array (programmable device) • Design stored in SRAM based memory • Single Event Upset Corrupt design Bit-flip in memory due to an ionizing particle

  5. Gate Source Drain N+ + - N+ + - + - + - + - + - + - + - + - + - + - + - + - + - P substrate SEU: The main concern for the TPC electronics • Basic mechanism • Charge particle depositing energy in a device through ionization • If Qdep > Qcrit => SEU Qdep

  6. Gate Source Drain N+ + - N+ + - + - + - + - + - + - + - + - + - + - + - + - + - P substrate SEU: The main concern for the TPC electronics • Basic mechanism • Charge particle depositing energy in a device through ionization • If Qdep > Qcrit => SEU • TPC radiation environment* • Energetic Hadrons (E > 20 MeV) • Nuclear Interaction • Short range recoil-ion, • Typically E < 10 MeV Qdep * Fasso et. at, Radiation in the ALICE TPC detector, ALICE internal Note-TRD 2003

  7. Gate Source Drain N+ + - N+ + - + - + - + - + - + - + - + - + - + - + - + - + - P substrate SEU: The main concern for the TPC electronics p • Basic mechanism • Charge particle depositing energy in a device through ionization • If Qdep > Qcrit => SEU • TPC radiation environment* • Energetic Hadrons (E > 20 MeV) • Nuclear Interaction • Short range recoil-ion, • Typically E < 10 MeV Si(p,p α)Mg p α Mg Qdep * Fasso et. at, Radiation in the ALICE TPC detector, ALICE internal Note-TRD 2003

  8. Irradiation Test Facilities • The Svedberg Laboratory, TSL • 38 & 180 MeV protons • 90 MeV neutrons • 106-107 p/cm2s &103-104 n/cm2s • Beam spot radius 2 & 15 cm • The Oslo Cyclotron, OCL • 29 MeV protons • 106-107 p/cm2s • Beam spot radius: 2 cm

  9. SEU Cross Section Result (Xilinx Virtex II Pro) • TSL (180 MeV p): σ = 2.14 x 10-14 cm2 / bit • OCL (29 MeV p): σ = 2.11 x 10-14 cm2 / bit • Independent experiment by Xilinx (atmospheric neutron spectra) • Rosetta+σ = 2.98 x 10-14 cm2 / bit • Scaled to the ALICE TPC radiation environment • Simulated* hadron flux 100-400 h/cm2s • Results per 216 FPGA / 4 hr unit Run • # SEU ~120 • # functional failures+ ~12 • Conservative numbers + Using an SEUPI: Single Event Upset Probability Impact = 10 Lesea et. al. The Rosetta Experiment, IEEE TRANS. ON DEVICE AND MATERIALS RELIABILITY, V 5, N3, 2005 *Fasso et. at, Radiation in the ALICE TPC detector, ALICE internal Note-TRD 2003

  10. Mitigation Results • Configuration memory is read back and bit-flips are corrected • The FPGA firmware design can be protected • Hamming bits • Triple Mode Redundancy • 1+2: Reduces the functional • failures to an acceptable level • Test flux: 106-107 p/cm2s • TPC flux: 100-400 h/cm2s • ~ factor 104 lower flux 1 2 3 1 1+2 No action Readback and Correction enabled Triple Modular Redundancy turned enabled

  11. 2. Next Step: SEU Modelling • Model the physical processes responsible for causing Single Event Upsets • 7 months research visit at IBM T.J. Watson Research Center, NY, USA(NFR Leiv Eiriksson mobilitetsstipend) • SEU modelling methodology • An important input is information about the target device • Layout and material (can be proprietary) • Some reverse engineering is needed

  12. FIB: Focused Ion Beam Target Device Information • Investiagated using Focused Ion Beam tool (FIB)

  13. Target Device Information: FIB Images ~5 um Device layer (90 nm transitors) Si substrate ~850 um Cu interconnet layer (0.4 um) FIB images are used to build a geometry model of our device

  14. + -+ - - - + - + - + - - + Modelling Methodology Describe physical processes • Inelastic and elastic Interactions • Nuclear fragmentation • Transportation Target information • Technology • Layout • Material Radiation environment • Particle type • Energy & flux Modelling Software Tool Radiation event generator Charge transport & collection Critical Charge < SEU

  15. Outlook • Radiation effects are becoming more important due to technology scaling • Lower Critical Charge for SEU -> more sensitive devices • The details of nuclear fragmentation will become more important • Potential new problem: Direct ionization from protons* • Multiple Bit Upsets (MBU): more frequent • Case study of FPGA • Variability study (layout geometry) • Compare with experimental results to validate method • Radiation environment • Add more detailed geometry of electronics rack • Update simulation results *Rodbell et al , Low-energy Proton induced Single Event Upsets in 65 nm…, Presented at NSREC July 2007

More Related