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EE 367 Logic Design

Lecture

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EE 367 Logic Design

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    1. Lecture #1 Page 1 EE 367 – Logic Design Spring 2008 EE 367 – Logic Design Lecture #1 Agenda Course Logistics Course Content Digital Review Announcements (Wednesday, 1/16) Welcome Homework #1 Posted (due Friday, 1/25) No Lab this Week

    2. Lecture #1 Page 2 EE 367 – Logic Design Spring 2008 Course Overview Instructor: Brock J. LaMeres Office : 533 Cobleigh Hall Phone : (406)-994-5987 Email : lameres@ece.montana.edu Web : www.coe.montana.edu/ee/lameres/ Time / Location: Lecture : MWF 11:00am – 11:50am 218 Roberts Lab -02 : W 2:10am – 4:00am 601 Cobleigh Hall Lab -03 : W 4:10am – 6:00am 601 Cobleigh Hall

    3. Lecture #1 Page 3 EE 367 – Logic Design Spring 2008 Course Overview Textbook: “Digital Design: Principles and Practices", 4th Addition John F. Wakerly, Prentice Hall, 2006 Website: www.coe.montana.edu/ee/lameres/courses/ee367_spring08 - all handouts, homework, and lab assignments are found here - it is your responsibility to download assignments

    4. Lecture #1 Page 4 EE 367 – Logic Design Spring 2008 Course Overview Office Hours: 533 Cobleigh Hall M, 3:00pm – 4:00pm F, 2:00pm – 3:00pm Also available by email appointment Requisites: EE262 / EE371 Grading: Homework - 10% Lab - 30% Exam #1 - 20% Exam #2 - 20% Design Project - 20% - Homework Assignments are due at the beginning of class. - Late homework will be accepted for one week after the due date with a penalty of 50% point reduction. No credit will be given for assignments over one week late. - No make up exams will be given. Plan on being available on the exam dates. - Final Design Project will be given instead of an in-class final.

    5. Lecture #1 Page 5 EE 367 – Logic Design Spring 2008 Course Overview Where does this course fit into the Electrical Engineering curriculum?

    6. Lecture #1 Page 6 EE 367 – Logic Design Spring 2008 Course Overview Where does this course fit into the Computer Engineering curriculum?

    7. Lecture #1 Page 7 EE 367 – Logic Design Spring 2008 Course Content What is this course? - In EE261 you learned: - basic combinational logic design - basic sequential logic design - In EE262 you learned: - how to implement logic circuits using off-the-shelf parts - EE367 is a follow-on course that looks at: - Large scale digital designs - Performance of digital circuitry - Programmable Logic

    8. Lecture #1 Page 8 EE 367 – Logic Design Spring 2008 Course Content What does "Large" mean? - Large means that you can't do it by hand. We need a way to design and simulate Millions of gates - K-maps for a Pentium would take too much paper

    9. Lecture #1 Page 9 EE 367 – Logic Design Spring 2008 Course Content We will learn VHDL in order to describe large digital designs - VHDL is a text based Hardware Description Language - We can simulate our digital designs created in VHDL

    10. Lecture #1 Page 10 EE 367 – Logic Design Spring 2008 Course Content We can also prototype our designs using an FPGA - FPGA = Field Programmable Gate Array - An FPGA is a programmable logic device - In Lab, we will implement our designs and test them in FPGA hardware

    11. Lecture #1 Page 11 EE 367 – Logic Design Spring 2008 Course Content What topics will be covered? 1) VHDL (Exam #1 Topics) 2) Medium Scale Combinational Logic Devices 3) More Complex Finite State Machines (Exam #2 Topics) 4) Computer Systems 5) FPGA Timing and Implementation Instead of a final, we will have a final project ex) - 4-bit microprocessor - peripheral controller (USB, Ethernet, RS232) - memory controller (EEprom, DDR, SRAM)

    12. Lecture #1 Page 12 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review Combinational Logic Combinational Logic Gates : - Output depends on the logic value of the inputs - no storage

    13. Lecture #1 Page 13 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review NOT out = in’ = in f(in) = in’ = in OR out = a+b f(a,b) = a+b AND out = a·b f(a,b) = a·b

    14. Lecture #1 Page 14 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review XOR out = a?b f(a,b) = a?b NOR out = a+b f(a,b) = a+b NAND out = a·b f(a,b) = a·b

    15. Lecture #1 Page 15 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review XNOR out = a?b f(a,b) = a?b Also remember about XOR Gates: f(a,b) = a?b = (a’b + b’a) Also remember the priority of logic operations (without parenthesis) is: NOT, AND, OR

    16. Lecture #1 Page 16 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review DeMorgan’s Theorems Inverting the output of any gate results in the same function as the opposite gate (AND/OR) with inverted inputs

    17. Lecture #1 Page 17 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review DeMorgan’s Theorems Graphically : breaking the bar changes the logic function (AND-OR) under the break

    18. Lecture #1 Page 18 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review Boolean Expressions Using SOP Logic functions can be described using a Sum of Products techniques Sum of Products (SOP) is the summation of all minterms resulting in the truth table A minterm is the expression for an input configuration which yields a TRUE output A minterm expression is the AND’ing of the input "1" signal configuration

    19. Lecture #1 Page 19 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review Boolean Expressions Using POS Logic functions can be described using a Product of Sums techniques Product of Sums (POS) is the multiplication of all maxterms resulting in the truth table A maxterm is the expression for an input configuration which yields a FALSE output A maxterm expression is the OR’ing of the input "0" signal configuration

    20. Lecture #1 Page 20 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review Boolean Expressions Using SOP & POS SOP and POS functions are equivalent

    21. Lecture #1 Page 21 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review Karnaugh Maps K-maps provide a graphical method to find SOP/POS expressions K-maps also provide a graphical method to perform logic minimization K-map SOP Process 1) Circle minterms to create SOP 2) Circle in Horizontal & Vertical manner 3) Circle in groups with powers of 2 (1,2,4,8,…)

    22. Lecture #1 Page 22 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review Karnaugh Maps K-maps provide a graphical method to find SOP/POS expressions K-maps also provide a graphical method to perform logic minimization K-map POS Process 1) Circle maxterms to create SOP 2) Circle in Horizontal & Vertical manner 3) Circle in groups with powers of 2 (1,2,4,8,…)

    23. Lecture #1 Page 23 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review Sequential Logic - Concept of “Storage Element” - With Storage, logic functions can depend on current & past values of inputs - Sequential State Machines can be created D-Flip-Flop - on timing event (i.e., edge of clock input), D input goes to Q output

    24. Lecture #1 Page 24 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review State Machines - Moore : Outputs depend on present state - Mealy : Outputs depend on present state and current inputs

    25. Lecture #1 Page 25 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review State Machine Example : Design a 2-bit Gray Code Counter

    26. Lecture #1 Page 26 EE 371 – Microprocessor HW & SW Systems Fall 2006 Digital Review State Machine Example : Design a 2-bit Gray Code Counter

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