Using Structural Relations for Checking Combinationality of C yclic C ircuits

1. Using Structural Relations for Checking Combinationality of Cyclic Circuits Wan-Chen Weng Date: 2014/06/19

2. Outline • Motivation • Problem formulation • Combinationality • Methodology • Outer and Inner Side Input • Loop backtracking • Self-conflictSide Input • Pre-clause • Program flow • Experimental results • Conclusion

3. Motivation(1/4) • S. Malik (1994) • For the analysis of cyclic circuits. • Ternary symbolic simulation. • Let  denote the unknown value.

4. Motivation(2/4) • Marc D. Riedel (2008) • SAT-based dual-rail model checking for the combinationality of cyclic circuits. • Add dummy variables and equivalent checkers to the corresponding module.

5. Motivation(3/4) • Marc D. Riedel (2008) • The original circuit will be combinational when SAT = 0.

6. Motivation(4/4) f = ab a b 3 variables 3 clauses f a1 a0 b1 b0 f1= a1b1+ a0b1b0’ f0 = a0b0+ a1b1’b0 10 variables 20clauses f1 f0 • Dual-rail model

7. Problem formulation(1/1) • Given: • a cyclic circuit C. • Determine: • if C is combinational. • By using: • And-inverter graph (AIG). • SAT-based approaches describing non-combinational relations between nodes in strongly connected components (SCCs). • If: • SAT, then at least one true loop exists. non-combinational • UNSAT, then all loops are false. combinational

8. Combinationality(1/8) CV False loop SCC • Stephen A. Edwards (2003) • An SCC is combinational at least one input to a gate is controlling value (CV). • SCC is combinational = every loop in the SCC is false • SCC is combinational every loop in the SCC is false. • every loop in the SCC is false SCC is combinational.

9. Combinationality(2/8) Loop with unknown signals SCC • An SCC is combinational • By definition of combinational behavior, every gate outputs a definite value. • Initially, outputs of gates from an SCC are simulated as unknown.

10. Combinationality(3/8) CV Loop with unknown signals false loop SCC SCC • An SCC is combinational • Base case 1: • If # of loops = 1 and only 1 controlling external input

11. Combinationality(4/8) CV CV CV L1 L2 L1 L1 L2 L2 SCC SCC SCC • An SCC is combinational • Base case 2: • If # of loops = 2 and 1 controlling external input

12. Combinationality(5/8) CV CV CV L1 ~ Lk Lk+1 L1 ~ Lk Lk+1 L1 ~ Lk Lk+1 SCC SCC SCC • An SCC is combinational • Assume # of loops = k holds, then # of loops = k+1:

13. Combinationality(6/8) • An SCC is combinational • By induction, every loop is false. • SCC is combinational every loop in the SCC is false.

14. Combinationality(7/8) • Every loop in the SCC is false • Initially, internal signals of every loop are unknown. At least one side input of every loop is CV. Every gate in any loop outputs a definite value. Every gate in the SCC outputs a definite value. SCC is combinational. • Every loop in the SCC is false SCC is combinational.

15. Combinationality(8/8) • Every loop in the SCC is false SCC is combinational. • SCC is non-combinational at least one loop is true. • SCC is combinational every loop in the SCC is false. • Exists a true loop in the SCC SCC is non-combinational.

16. Outer and Inner Side Input (1/4) A L1 B S1 n3 n1 n1 A L2 n1 n4 n4 n4 n2 n2 n2 B B n3 n3 C C

17. Outer and Inner Side Input (2/4) • Distinguish between external inputs and internal signals: • Outer side inputs (OSIs): • side inputs entirely from somewhere outside the SCC. • A, B, C. • Inner side inputs (ISIs): • side inputs from somewhere inside the SCC. • n1, n3. 17

18. Outer and Inner Side Input (3/4) • (OSIx_1∧ … ∧OSIx_n∧ ISIx_1∧ … ∧ISIx_n) • = (NCV ∧ … ∧NCV ∧NCV ∧ … ∧NCV) • (loopy_1∨ …∨loopy_x∨ … ∨ loopy_n) = SAT • Non-combinational relations: • For a loop Lx: • For an SCCy:

19. Outer and Inner Side Input (4/4) • Problems remain: • How to check if ISIs are definite? • What relation can judge oscillations between logical 0 and 1?

20. Loop backtracking (1/6) Clause of the loop (OSIs/ISIs): (A ∧ B) Clause of n1, n2: n1 = A‧n2 (A∨n2∨n1)∧ (A∨n1) ∧ (n2∨n1) n2 = B‧n1 (B∨n1∨n2)∧ (B∨n2) ∧ (n1∨n2) Results: [SAT] (n1, n2) = (0, 0) or (1, 1) n2 A B n1

21. Loop backtracking (2/6) if (A, B) = (NCV, NCV) then (n1, n2) = (1/0, 0/1) or (n1, n2) = (0/1, 1/0). Clause of n1, n2: n1 = A‧n2 (A∨n2∨n1)∧ (A∨n1) ∧ (n2∨n1) n2 = B‧n1 (B∨n1∨n2)∧ (B∨n2) ∧ (n1∨n2) Results: [UNSAT] n2 A B n1

22. Loop backtracking (3/6) • The weakness of SAT solvers • No timing concept. • Cannot detect  happened across time frames. • Can only distinguish the uncertainty but oscillations. • Notation • Time differential : T.

23. Loop backtracking (4/6) nT-1 nT To represent the value of a node in T and T-1, we derive an equation with its fanins and trace back the fanin cone until the node be reached again as well as all variables in the equation are not in time T.

24. Loop backtracking (5/6) SCC SCC path 1 Condition: n should be 1 Time tag: T-1 nT nT Fin_cone Condition: n should be 0 Time tag: T

25. Loop backtracking (6/6) SCC SCC SCC path 1 path 1 Condition: n should be 1 Time tag: T-1 path 2 path 2 SCC path 1 nT nT nT nT Fin_cone Condition: n should be 0 Time tag: T-2

26. Self-conflictSide Input (1/1) nx n3 n2 n4 n1 Side input nx always breaks the loop.

27. Pre-clause (1/1) nx ny A Original clauses: (A…∧ … ∧ …) ∨ (B…∧ … ∧ …) Pre-clause: (A∨ B) ∧ … ∧ … Cycle 1 Cycle 2 B • Cycles may converge and share same nodes. • Side inputs may appear in different cycles repetitively. • Extract non-shared side inputs to lower the SAT-solving cost.

28. Program flow (1/1) Cyclic circuit C NO Find an SCC S All SCCs are checked? Find all loop L in S YES Side input searching for each loop of L Self-conflict detection for L SAT solving All loops are self-conflict? YES termination NO Pre-clause Loop-backtracking NO YES Exists un-tracing SCC?

29. Experimental results (1/1)

30. Conclusion (1/1) We proposed a SAT-based approach that deals with structural relations instead of duplicating signals, and it is scalable for circuits up to tens of thousands of gated. We filtered out certain cycles before SAT solving, raising the validation speed.